MEMORY CIRCUIT AND A TRACKING CIRCUIT THEREOF

• US 20120163109A1
• Filed: 12/28/2010
• Published: 06/28/2012
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Narayanaswamy, Santhosh, Gupta, Sharad, Holla, Lakshmikantha V.
• Granted Patent: US 8,320,210 B2
• Time in Patent Office: Days
• US Class Current: 365/203
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell.

Claims

1. A tracking circuit comprising:

a dummy bit line;

a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal, wherein the wordline activation signal causes activation of a memory cell; and

a second circuit responsive to discharge of the dummy bit line to enable access to the memory cell.

2. The tracking circuit as claimed in claim 1, wherein the first signal is indicative of voltage of an array header of a memory circuit, wherein the memory circuit comprises the memory cell.

3. The tracking circuit as claimed in claim 1, wherein the first circuit comprises:

a third circuit to detect activation of a wordline and to generate the wordline activation signal in response to detection; and

a plurality of transistors in series connection to discharge the dummy bit line in response to the first signal and the wordline activation signal.

4. The tracking circuit as claimed in claim 3, wherein the third circuit comprises:

an electrical line;

a first negative metal oxide semiconductor (NMOS) transistor, having a gate coupled to the wordline and a drain coupled to the electrical line, to discharge the electrical line in response to the activation of the wordline; and

a fourth circuit to generate the wordline activation signal in response to the discharge of the electrical line.

5. The circuit as claimed in claim 4, wherein the fourth circuit comprises:

a fifth circuit that is similar to a wordline driver of the wordline;

two pairs of cross-coupled positive metal oxide semiconductor (PMOS) transistors each pair comprising at least one PMOS transistor having a gate coupled to an output of the fifth circuit to precharge the electrical line, and

a NAND gate coupled to the electrical line to generate the wordline activation signal in response to the discharge of the electrical line.

6. The tracking circuit as claimed in claim 4, wherein the fourth circuit comprises

an inverter to invert the voltage of the electrical line.

7. The tracking circuit as claimed in claim 1, wherein the first circuit is coupled to a retention-till-access (RTA) switch, the RTA switch generating the first signal.

8. The tracking circuit as claimed in claim 1, wherein the second circuit enables access to the memory cell at a desired time by introducing a delay between time of discharge of the dummy bit line and time to access the memory cell.

9. The tracking circuit as claimed in claim 1, wherein the second circuit comprises an inverter to invert voltage of the dummy bit line.

10. The tracking circuit as claimed in claim 9, wherein the second circuit further comprises:

a first pair of negative metal oxide semiconductor (NMOS) transistors in series connection, the first pair of NMOS transistors comprising

a first NMOS transistor having gate coupled to a peripheral voltage supply and having drain coupled to the dummy bit line, and

a second NMOS transistor having gate coupled to the peripheral voltage supply and having source coupled to the inverter; and

a second pair of negative metal oxide semiconductor (NMOS) transistors in parallel connection with the first pair of NMOS transistors, the second pair of NMOS transistors comprising

a third NMOS transistor having gate coupled to an array voltage supply and having drain coupled to the dummy bit line, and

a fourth NMOS transistor having gate coupled to the array voltage supply and having source coupled to the inverter.

11. The tracking circuit as claimed in claim 1, wherein the second circuit is coupled to a pulse generator, the pulse generator being responsive to the discharge of the dummy bit line to render a sense amplifier to access the memory cell.

12. A memory circuit comprising:

a clock circuit to generate a first clock signal and a second clock signal;

a retention-till-access switch, responsive to the second clock signal, to generate a first signal and a wordline header signal;

a wordline driver, responsive to the first clock signal and to the wordline header signal, to drive a wordline to render a memory cell to be ready for access;

a first circuit, responsive to the second clock signal and to the wordline header signal, to track a wordline path from the clock circuit to the wordline and to generate a wordline activation signal;

a dummy bit line to discharge through the first circuit based on a logical combination of the first signal and the wordline activation signal;

a second circuit responsive to discharge of the dummy bit line to generate a second signal based on peripheral voltage supply variations;

a pulse generator responsive to the second signal to generate an enable signal; and

a sense amplifier responsive to the enable signal to access the memory cell.

13. The memory circuit as claimed in claim 12 and further comprising:

a positive metal oxide semiconductor (PMOS) transistor configured to precharge the dummy bit line based on a delayed version of the second clock signal.

14. The memory circuit as claimed in claim 12, wherein the memory circuit is comprised in one of:

a static random access memory circuit; and

a memory cache of a processor.

15. The memory circuit as claimed in claim 12, wherein the clock circuit comprises:

two inverters in series connection to generate the second clock signal.

16. A method comprising:

generating a wordline activation signal in response to activation of a wordline;

discharging a dummy bit line based on a logical combination of a first signal and the wordline activation signal; and

enabling access to a memory cell, coupled to the wordline, in response to the discharging.

17. The method as claimed in claim 16, wherein the first signal is indicative of voltage of an array header of the memory circuit.

18. The method as claimed in claim 16 and further comprising:

generating a first clock signal and a second clock signal;

generating, based on the second clock signal, the first signal and a wordline header signal; and

activating the wordline based on the wordline header signal and the first clock signal.

19. The method as claimed in claim 16, wherein enabling access to the memory signal comprises inverting voltage of the dummy bit line based on peripheral voltage supply of the memory circuit.