METHOD AND APPARATUS TO PROVIDE A HIGH AVAILABILITY SOLID STATE DRIVE

• US 20120166699A1
• Filed: 12/22/2010
• Published: 06/28/2012
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Mitchell, James, Kumar, Panakaj
• Granted Patent: US 8,589,723 B2
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A method and apparatus to use Solid State Drives (SSD) in a high availability enterprise system is provided. Concurrent redundant paths are provided to the SSD to at least two storage controllers via a serial system bus using a non-storage bus protocol.

Claims

1. An apparatus comprising:

a non-volatile memory organized as block storage; and

logic coupled to the non-volatile memory, the logic to provide concurrent redundant paths to the non-volatile memory to one of at least two storage controllers coupled via a serial system bus to the logic, the storage controllers and logic to communicate via the serial system bus using a non-storage bus protocol.

2. The apparatus of claim 1, wherein the system bus uses a Peripheral Component Interconnect Express (PCIe) bus protocol.

3. The apparatus of claim 2, wherein the logic is included in a first Printed Circuit Board (PCB) and the non-volatile memory is included in a second PCB, the first PCB includes a first connector to couple to the second PCB and the first PCB includes at least two second connectors, each second connector to couple to one of the storage controllers.

4. The apparatus of claim 1, wherein the logic and non-volatile memory are in a solid state drive (SSD) and the logic includes at least two connectors, each connector to couple to one of the one of the storage controllers.

5. The apparatus of claim 1, wherein the logic includes a Multi Root-Input Output Virtualization (MR-IOV) logic to switch access to the non-volatile memory from a first storage controller to a second storage controller upon detecting a failure in the first storage controller.

6. The apparatus of claim 1, wherein the storage controllers to communicate via a PCIe Non-Transparent Bridge (NTB) link.

7. The apparatus of claim 6, wherein each of the storage controllers includes a Direct Memory Access Controller (DMAC), the DMAC to concurrently move data to a memory in a first storage controller and to send the data via the PCIe NTB link to a second storage controller for mirroring in memory in the second storage controller.

8. A method comprising:

organizing a non-volatile memory as block storage;

providing, by logic coupled to the non-volatile memory, concurrent redundant paths to the non-volatile memory to one of at least two storage controllers coupled via a serial system bus to the logic; and

communicating, by the storage controllers via the serial system bus using a non-storage bus protocol.

9. The method of claim 8, wherein the system bus uses a Peripheral Component Interconnect Express (PCIe) bus protocol.

10. The method of claim 9, wherein the logic is included in a first Printed Circuit Board (PCB) and the non-volatile memory is included in a second PCB, the first PCB includes a first connector to couple to the second PCB and the first PCB includes at least two second connectors, each second connector to couple to one of the storage controllers.

11. The method of claim 8, wherein the logic and non-volatile memory are in a solid state drive (SSD) and the logic includes at least two connectors, each connector to couple to one of the one of the storage controllers.

12. The method of claim 8, wherein the logic includes a Multi Root-Input Output Virtualization (MR-IOV) logic to switch access to the non-volatile memory from a first storage controller to a second storage controller upon detecting a failure in the first storage controller.

13. The method of claim 8, wherein the storage controllers to communicate via a PCIe Non-Transparent Bridge (NTB) link.

14. The method of claim 13, wherein each of the storage controllers includes a Direct Memory Access Controller (DMAC), the DMAC to concurrently move data to a memory in a first storage controller and to send the data via the PCIe NTB link to a second storage controller for mirroring in memory in the second storage controller.

17. The method of claim 8, wherein the storage controllers to communicate via a PCIe Non-Transparent Bridge (NTB) link.

18. The method of claim 13, wherein each of the storage controllers includes a Direct Memory Access Controller (DMAC), the DMAC to concurrently move data to a memory in a first storage controller and to send the data via the PCIe NTB link to a second storage controller for mirroring in memory in the second storage controller.

15. An article including a machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:

organizing a non-volatile memory as block storage;

providing, by logic coupled to the non-volatile memory, concurrent redundant paths to the non-volatile memory to one of at least two storage controllers coupled via a serial system bus to the logic; and

communicating, by the storage controllers via the serial system bus using a non-storage bus protocol.

16. The article of claim 15, wherein the system bus uses a Peripheral Component Interconnect Express (PCIe) bus protocol.

19. A system comprising:

at least two storage controllers;

a non-volatile memory organized as block storage; and

logic coupled to the non-volatile memory, the logic to provide concurrent redundant paths to the non-volatile memory to one of at the at least two storage controllers coupled via a serial system bus to the logic, the storage controllers and logic to communicate via the serial system bus using a non-storage bus protocol.

20. The system of claim 19, wherein the storage controllers to communicate via a PCIe Non-Transparent Bridge (NTB) link, each of the storage controllers includes a Direct Memory Access Controller (DMAC), the DMAC to concurrently move data to a memory in a first storage controller and to send the data via the PCIe NTB link to a second storage controller for mirroring in memory in the second storage controller.