DECENTRALIZED POWER MANAGEMENT DISTRIBUTED AMONG MULTIPLE PROCESSOR CORES

• US 20120166837A1
• Filed: 11/17/2011
• Published: 06/28/2012
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Darius D.
• Granted Patent: US 8,635,476 B2
• Time in Patent Office: Days
• US Class Current: 713/321
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-core processor provides a configurable resource shared by two or more cores, wherein configurations of the resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate. Internal core power state management logic configures each core to participate in a de-centralized inter-core power state discovery process to discover a composite target power state for the shared resource that is a most restrictive or power-conserving state that will not interfere with any of the corresponding target power states of each core sharing the resource. The internal core power state management logic determines whether the core is a master core authorized to configure the resource, and if so, configures that resource in the discovered composite power state. The de-centralized power state discovery process is carried out between the cores on sideband, non-system bus wires, without the assistance of centralized non-core logic.

Claims

1. A multi-core processor comprising:

a plurality of enabled physical processing cores;

a configurable resource shared by two or more of the cores, wherein configurations of the shared resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate;

for each core, internal core power state management logic configuring the core to participate in a de-centralized inter-core power state discovery process carried out between the cores without the assistance of centralized non-core logic;

wherein the internal core power management logic is duplicated in each core;

wherein the internal core power management logic configures the core to instigate implementation of a composite target power state for configuring the shared resource, if the core is designated as a master core for the purpose of configuring the shared resource and the composite target power state is discovered through the de-centralized inter-core power state discovery process;

wherein the composite target power state is a most power-conserving power state for the shared resource that will not interfere with any corresponding target power state of each core sharing the resource

2. The multi-core processor of claim 1, further comprising sideband communication wires, distinct from a system bus connecting the cores to a chipset, between the cores, and wherein de-centralized inter-core power state discovery processes are carried with power state values exchanged between the cores over the sideband communication wires.

3. The multi-core processor of claim 1, wherein:

the target power states are C-states;

the shared resource is a system bus, shared by all of the cores, and connected to a chipset; and

the master core monopolizes coordination with the chipset to implement a C-state affecting operation of the bus.

4. The multi-core processor of claim 1, wherein:

the shared resource is a voltage source shared by at least some of the cores;

a target power state is indicated by a requested voltage change request signal; and

the master core monopolizes voltage change request signals sent to the voltage source requesting a change in a voltage level supplied to the cores sharing the voltage source.

5. The multi-core processor of claim 1, wherein:

the shared resource is a clock source shared by at least some of the cores;

a target power state is indicated by a requested clock ratio signal; and

the master core monopolizes clock ratio request signals sent to the clock source that would result in a change of clock frequency supplied by the clock source to the cores sharing the clock source.

6. The multi-core processor of claim 1, wherein:

only a single one of the cores sharing the resource is designated as the master core for purposes of instigating implementation of the composite target power state; and

the cores include programmable logic enabling it to be configured, via system software, to add or remove a master designation for purposes of configuring the shared resource.

7. The multi-core processor of claim 6, wherein the internal core power management logic is configured to evaluate the programmable logic to determine whether its core is the designated master for purposes of instigating implementation of the composite target power state.

8. The multi-core processor of claim 1, wherein a target power state is one of a plurality of predefined power states for which the power state management logic is configured to instigate an implementation, wherein the plurality of predefined power states includes at least one unrestricted power state affecting an unshared resource, internal to the core, and the internal core power management logic of each core is configured to implement, without inter-core coordination, a native core target power state if it is an unrestricted power state.

9. The multi-core processor of claim 1, wherein the power state management logic configures each core to invoke the de-centralized inter-core power state discovery process in response to receiving a request to transition into a target power state that would configure the shared resource.

10. The multi-core processor of claim 1, wherein the power state management logic configures each core to participate in an externally invoked de-centralized inter-core power state discovery process.

11. The multi-core processor of claim 1, wherein a de-centralized inter-core power state discovery process comprises a plurality of synchronized instances of identical inter-core power state discovery microcode, executed on each of the cores participating in the process, exchanging power states.

12. The multi-core processor of claim 11, wherein each instance of inter-core power state discovery microcode native to a given core exchanges a power state with another core;

and wherein the native instance calculates a compound power state as a function of at least two of the following values;

the native core target power state, if any, a probe power state value received by an invoking process, and a power state value returned from a dependently invoked instance of the inter-core power state discovery microcode.

13. The multi-core processor of claim 11, wherein the de-centralized inter-core power state discovery process comprises instances of the inter-core power state discovery microcode recursively invoking and synchronizing with dependent instances of the inter-core power state discovery microcode on other cores sharing the shared resource through a hierarchical path of interconnected cores.

14. A decentralized method of managing power states for a multi-core processor, the multi-core processor having a plurality of enabled physical cores and a resource shared by at least some of the cores, the method comprising:

a core receiving a native core target power state affecting a configurable resource shared between itself and at least one other core, wherein the native core target power state defines a configuration of the resource that would affect the power, speed, or efficiency with which the cores sharing the resource would be able to operate;

the core participating in an inter-core power state discovery process that comprises an exchange, unmediated by any centralized non-core logic, of power states with at least one other core sharing the resource; and

the core instigating implementation of a composite target power state for configuring the shared resource, if the core is designated as a master core for the purpose of configuring the shared resource and the composite target power state is discovered through the de-centralized inter-core power state discovery process;

wherein the composite target power state is a most power-conserving power state for the shared resource that will not interfere with any corresponding target power state of each core sharing the resource.

15. The method of claim 14, further comprising participating in the inter-core power state discovery process through sideband communication wires between the cores, wherein the sideband communication wires are distinct from a system bus connecting the cores to a chipset, and wherein power states exchanged between the cores are exchanged over the sideband communication wires.

16. The method of claim 14, wherein:

the target power states are C-states;

the shared resource is a system bus, shared by all of the cores, and connected to a chipset; and

the master core monopolizes coordination with the chipset to implement a C-state affecting operation of the bus.

17. The method of claim 14, wherein:

the shared resource is a voltage source shared by at least some of the cores;

a target power state is indicated by a requested voltage change request signal; and

the master core monopolizes voltage change request signals sent to the voltage source requesting a change in a voltage level supplied to the cores sharing the voltage source.

18. The method of claim 14, wherein:

the shared resource is a clock source shared by at least some of the cores;

a target power state is indicated by a requested clock ratio signal; and

the master core monopolizes clock ratio request signals sent to the clock source that would result in a change of clock frequency supplied by the clock source to the cores sharing the clock source.

19. The method of claim 14, further comprising:

the master core, through participation in an inter-core power state discovery process invoked by another core, discovering and instigating implementation of a composite target power state for configuring the shared resource.

20. Microcode encoded in a computer readable storage medium of a physical core of a multi-core processor, the microcode comprising code for:

receiving a request to configure a configurable resource shared by two or more of the cores, wherein configurations of the shared resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate;

participating in a de-centralized inter-core power state discovery process carried out between the cores without the assistance of centralized non-core logic; and

configuring the core to instigate implementation of a composite target power state for configuring the shared resource, if the core is designated as a master core for the purpose of configuring the shared resource and the composite target power state is discovered through the de-centralized inter-core power state discovery process;

wherein the composite target power state is a most power-conserving power state for the shared resource that will not interfere with any corresponding target power state of each core sharing the resource.