POWER STATE SYNCHRONIZATION IN A MULTI-CORE PROCESSOR
First Claim
1. A multi-core processor comprising:
- a plurality of physical processing cores; and
inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores.
1 Assignment
0 Petitions
Accused Products
Abstract
A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications.
59 Citations
26 Claims
-
1. A multi-core processor comprising:
-
a plurality of physical processing cores; and inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A decentralized, microcode-implemented method of discovering states of a multi-core processor comprising a plurality of physical processing cores, the method comprising:
at least two cores participating in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, exchanged by the cores. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25)
-
26. A microcode routine encoded in a computer readable storage medium of a physical core of a multi-core processor, the microcode routine comprising code for discovering an applicable state of the multi-core processor using a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, exchanged by the cores;
wherein the applicable state is one of the following states; a composite power state for the processor; a composite power state for a domain of the processor, the domain comprising a group of cores that share a configurable resource operable to be configured, for purposes of power conservation, according to one of a plurality of configurations; a target power state of another core; a least restrictive target power state of any of a group of cores sharing a configurable resource; a most restrictive operating state that can be implemented by a core without interfering with corresponding target operating states of other cores; whether a core is enabled or disabled; how many cores of the multi-core processor are enabled; an identification of shared resources and domains of cores amongst which various configurable resources are shared; a hierarchical coordination system of the cores used for managing shared resources; an availability within the multi-core processor of sideband communication wires to coordinate cores, which sideband communication wires are independent of a system bus connecting the multi-core processor to a chipset; and a hierarchical coordination system of the cores applied to inter-core communications over sideband communication wires that are independent of a system bus connecting the multi-core processor to a chipset.
Specification