LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) HAVING A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE (Vb), A METHOD OF FORMING AN LEDMOSFET, AND A SILICON-CONTROLLED RECTIFIER (SCR) INCORPORATING A COMPLEMENTARY PAIR OF LEDMOSFETS

• US 20120168817A1
• Filed: 09/21/2011
• Published: 07/05/2012
• Est. Priority Date: 01/03/2011
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Abou-Khalil, Michel J., Botula, Alan B., Joseph, Alvin J., Letavic, Theodore J., Slinkman, James A.
• Granted Patent: US 8,901,676 B2
• Time in Patent Office: Days
• US Class Current: 257/133
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7436 Lateral thyristors
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs.

Claims

1. A field effect transistor comprising:

a semiconductor body comprising;

a channel region;

a drain region;

a drain drift region between said channel region and said drain region; and

conductive field plates adjacent to opposing sides of said drain drift region, each having a sidewall angled relative to said drain drift region such that an area between said drain drift region and said conductive field plate has a continuously increasing width along a length of said drain drift region from adjacent said channel region to adjacent said drain region.

2. The field effect transistor of claim 1, said conductive field plates comprising any one of the following:

discrete polysilicon structures;

discrete metal structures; and

doped regions of said semiconductor body.

3. The field effect transistor of claim 2, said doped regions having a different conductivity type than said drain region.

4. The field effect transistor of claim 1, said area comprising any one of the following:

a portion of a trench isolation region defining said semiconductor body; and

a depletion region of said semiconductor body.

5. The field effect transistor of claim 1, said sidewall being essentially linear such that said area has a linearly increasing width.

6. The field effect transistor of claim 1, said area having predefined dimensions to ensure that said drain drift region has an essentially uniform horizontal electric field profile from said channel region to said drain region.

7. The field effect transistor of claim 1, said area having predefined dimensions to ensure that said field effect transistor has a specific drain-to-body breakdown voltage.

8. A method of forming a field effect transistor, said method comprising:

forming a trench isolation region to define a semiconductor body in a semiconductor layer; and

forming conductive field plates adjacent to opposing sides of a drain drift region in said semiconductor body, each conductive field plate having a sidewall angled relative to said drain drift region such that an area between said drain drift region and said conductive field plate has a continuously increasing width along a length of said drain drift region from adjacent a channel region in said semiconductor body to adjacent a drain region in said semiconductor body.

9. The method of claim 8, said forming of said trench isolation region being performed such that said semiconductor body has an essentially rectangular shape.

10. The method of claim 8, said forming of said conductive field plates comprising forming any one of discrete polysilicon structures and discrete metal structures on said trench isolation region.

11. The method of claim 8, said forming of said conductive field plates comprising forming any one of discrete polysilicon structures and discrete metal structures extending vertically through said trench isolation region.

12. The method of claim 8, said forming of said conductive field plates being performed such that said sidewall is essentially linear and, thereby such that said area has a linearly increasing width.

13. The method of claim 8, further comprising predefining dimensions of said area to ensure that said drain drift region has an essentially uniform horizontal electric field profile from said channel region to said drain region.

14. The method of claim 13, said predefining of dimensions of said area being performed to further ensure that said field effect transistor has a specific drain-to-body breakdown voltage.

15. A method of forming a field effect transistor, said method comprising:

forming a trench isolation region to define a semiconductor body in a semiconductor layer, said semiconductor body having a main portion and additional portions that extend laterally from opposing sides of said main portion; and

forming a plurality of dopant implant regions in said semiconductor body so as to form, in said main portion, a channel region, a drain region, and a drain drift region between said channel region and said drain region,

said forming of said plurality of dopant implant regions further being performed so as to form, in said additional portions, conductive field plates adjacent to said opposing sides of said drain drift region, each conductive field plate having a sidewall angled relative to said drain drift region such that an area between said drain drift region and said conductive field plate forms a depletion region having a continuously increasing width along a length of said drain drift region from adjacent said channel region to adjacent said drain region.

16. The method of claim 15, said forming of said plurality of dopant implant regions being performed such that said conductive field plates have a different conductivity type than said drain region.

17. The method of claim 15, said forming of said plurality of dopant implant regions being performed such that said sidewall is essentially linear and, thereby such that said area has a linearly increasing width.

18. The method of claim 15, further comprising predefining dimensions of said area to ensure that said drain drift region has an essentially uniform horizontal electric field profile from said channel region to said drain region.

19. The method of claim 18, said predefining of said dimensions of said area being performed to further ensure that said field effect transistor has a specific drain-to-body breakdown voltage.

20. A silicon-controlled rectifier comprising:

a semiconductor body;

a first field effect transistor comprising;

a first channel region in said semiconductor body;

a first drain region in said semiconductor body;

a first drain drift region in said semiconductor body between said first channel region and said first drain region; and

first conductive field plates adjacent to first opposing sides of said first drain drift region, each first conductive field plate having a first sidewall angled relative to said first drain drift region such that a first area between said first drain drift region and said first conductive field plate has a continuously increasing first width along a first length of said first drain drift region from adjacent said first channel region to adjacent said first drain region; and

a second field effect transistor having a different type conductivity than said first field effect transistor, said second field effect transistor comprising;

a second channel region in said semiconductor body abutting said first channel region;

a second drain region in said semiconductor body;

a second drain drift region in said semiconductor body between said second channel region and said second drain region; and

second conductive field plates adjacent to second opposing sides of said second drain drift region, each second conductive field plate having a second sidewall angled relative to said second drain drift region such that a second area between said second drain drift region and said second conductive field plate has a continuously increasing second width along a second length of said second drain drift region from adjacent said second channel region to adjacent said second drain region.

21. The silicon-controlled rectifier of claim 20, further comprising a gate structure adjacent to both said first channel region and said second channel region.

22. The silicon-controlled rectifier of claim 21, said gate structure comprising a dual work function gate structure.

23. The silicon-controlled rectifier of claim 20, said first conductive field plates and said second conductive plates each comprising any of the following:

discrete polysilicon structures;

discrete metal structures; and

dopant implant regions in said semiconductor body.

24. The silicon controlled rectifier of claim 20, said first area and said second area each comprising any one of the following:

a portion of a trench isolation region; and

a depletion region of said in said semiconductor body.

25. The silicon-controlled rectifier of claim 20, said first sidewall and said second sidewall each being essentially linear such that said first area and said second area each have a linearly increasing width.