JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE

• US 20120168820A1
• Filed: 01/03/2011
• Published: 07/05/2012
• Est. Priority Date: 01/03/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Liu, Xuefeng, Phelps, Richard A., Rassel, Robert M., Tian, Xiaowei
• Granted Patent: US 8,754,455 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 27/14679 Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66916 with a PN heterojunction gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/8086 Thin film JFET's

Abstract

Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

Claims

1. A junction field effect transistor comprising:

an N-type channel region having a first end and a second end opposite said first end and further having a first side and a second side opposite said first side;

N-type source/drain regions adjacent to said first end and said second end;

a first P-type gate adjacent to said first side; and

a second P-type gate adjacent to said second side, wherein at least one of said first P-type gate and said second P-type gate comprises any one of silicon germanium and silicon germanium carbide.

2. The junction field effect transistor of claim 1, further comprising:

a substrate;

an insulator layer on said substrate; and

an N-type semiconductor layer on said insulator layer, said N-type source/drain regions comprising N-type implant regions in said semiconductor layer,

said N-type channel region comprising a portion of said semiconductor layer separating said N-type implant regions,

said first P-type gate comprising any one of a first P-type silicon germanium layer and a first P-type silicon germanium carbide layer filling a first trench that is positioned laterally adjacent to said first side of said N-type channel region, and

said second P-type gate comprising any one of the following;

a P-type implant region adjacent to said second side of said N-type channel region; and

any one of a second P-type silicon germanium layer and a second P-type silicon germanium carbide layer filling a second trench that is positioned laterally adjacent to said second side of said N-type channel region.

3. The junction field effect transistor of claim 1, further comprising:

a silicon substrate; and

a first N-well in said substrate,

said first P-type gate comprising a P-well in said substrate above and abutting said first N-well,

said N-type channel region comprising a second N-well in said substrate above and abutting said P-well, and

said second P-type gate comprising any one of a P-type silicon germanium layer and a P-type silicon germanium carbide layer filling a trench that extends vertically from a top surface of said substrate to said second N-well, said trench having a bottom surface that abuts said N-type channel region and is above and physically separated from said first P-type gate.

4. The junction field effect transistor of claim 3,

said N-type source/drain regions comprising N-type implant regions at said top surface of said substrate and abutting said N-type channel region,

said N-type implant regions having a higher concentration of an N-type dopant than said N-type channel region,

said second P-type gate being positioned laterally between said N-type implant regions, and

said field effect transistor further comprising isolation structures isolating said N-type implant regions from said second P-type gate.

5. The junction field effect transistor of claim 4, further comprising:

a first contact extending vertically from said top surface to said first P-type gate; and

a second contact extending vertically from said top surface to said first N-well.

6. The junction field effect transistor of claim 1, further comprising:

a silicon substrate; and

an N-well in said substrate,

said first P-type gate comprising any one of a first P-type silicon germanium layer and a first P-type silicon germanium carbide layer in a lower portion of a first trench that extends vertically from a top surface of said substrate to said N-well,

said N-type channel region comprising an N-type silicon layer in said first trench on said first P-type gate, and

said second P-type gate comprising a P-type semiconductor layer filling a second trench that extends vertically into said N-type silicon layer, said second trench having a bottom surface that abuts said N-type channel region and is above and physically separated from said first P-type gate.

7. The junction field effect transistor of claim 6, said P-type semiconductor layer comprising any one of a P-type silicon layer, a second P-type silicon germanium layer and a second P-type silicon germanium carbide layer.

8. The junction field effect transistor of claim 6,

said N-type source/drain regions comprising N-type implant regions at said top surface of said substrate abutting said N-type channel region,

said N-type implant regions having a higher concentration of an N-type dopant than said N-type channel region,

said second P-type gate being positioned laterally between said N-type implant regions, and

said field effect transistor further comprising isolation structures isolating said N-type implant regions from said second P-type gate.

9. The junction field effect transistor of claim 6, further comprising:

a first contact extending vertically from said top surface to said first P-type gate; and

a second contact extending vertically from said top surface to said N-well.

10. A method of forming a junction field effect transistor, said method comprising:

forming N-type source/drain regions adjacent to a first end of an N-type channel region and adjacent to a second end of an N-type channel region opposite said first end; and

forming a first P-type gate adjacent to a first side of said N-type channel region and a second P-type gate adjacent to a second side of said N-type channel region opposite said first gate such that at least one of said first P-type gate and said second P-type gate comprises any one of silicon germanium and silicon germanium carbide.

11. The method of claim 10, further comprising providing wafer comprising a substrate, an insulator layer on said substrate and an N-type semiconductor layer on said insulator layer, said forming of said N-type source/drain regions comprising forming N-type implant regions in said N-type semiconductor layer such that said N-type implant regions are separated by a designated portion of said N-type semiconductor layer comprising said N-type channel region.

12. The method of claim 10, said forming of said first P-type gate comprising:

forming a first trench positioned laterally adjacent to said first side of said N-type channel region; and

filling said first trench with any one of a first silicon germanium layer and a first silicon germanium carbide layer.

13. The method of claim 12, said forming of said second P-type gate comprising any one of the following:

forming a P-type implant region in said N-type semiconductor layer adjacent to said second side of said N-type channel region; and

essentially simultaneously with said forming of said first P-type gate, forming a second trench positioned laterally adjacent to said second side of said N-type channel region and filling said second trench with any one of a second silicon germanium layer and a second silicon germanium carbide layer.

14. A method of forming a junction field effect transistor, said method comprising:

providing a silicon substrate;

forming a first N-well in said substrate;

forming a first P-type gate for said junction field effect transistor, said forming of said first P-type gate comprising forming a P-well in said substrate above and abutting said first N-well;

forming an N-type channel region for said junction field effect transistor, said forming of said N-type channel region comprising forming a second N-well in said substrate above and abutting said P-well; and

forming a second P-type gate for said junction field effect transistor, said forming of said second P-type gate comprising;

forming a trench that extends vertically from said top surface of said substrate to said second N-well, said trench having a bottom surface that abuts said N-type channel region and is above and physically separated from said first P-type gate; and

filling said trench with any one of a silicon germanium layer and a silicon germanium carbide layer.

15. The method of claim 14, further comprising, forming N-type source/drain regions for said junction field effect transistor, said forming of said N-type source/drain regions comprising forming N-type implant regions at said top surface of said substrate, said N-type implant regions being formed so as to abut said N-type channel region, so as to have a higher concentration of an N-type dopant than said N-type channel region and so that said second P-type gate is positioned laterally between said N-type implant regions;

and

forming isolation structures so that said N-type source/drain regions are isolated from said second P-type gate.

16. The method of claim 14, further comprising:

forming a first contact extending vertically from said top surface to said first P-type gate; and

forming a second contact extending vertically from said top surface to said first N-well.

17. The method of claim 16, said first contact being formed so as to be electrically connected to said second P-type gate.

18. A method of forming a junction field effect transistor, said method comprising:

comprising;

providing a silicon substrate;

forming an N-well in said substrate;

forming a first trench that extends vertically from a top surface of said substrate into said N-well;

forming a first P-type gate for said junction field effect transistor, said forming of said first P-type gate comprising forming any one of a first P-type silicon germanium layer and a first P-type silicon germanium carbide layer in a lower portion of said first trench;

forming an N-type channel region for said junction field effect transistor, said forming of said N-type channel region comprising forming an N-type silicon layer in said first trench on said first P-type gate; and

forming a second P-type gate for said junction filed effect transistor, said forming of said P-type gate comprising;

forming a second trench extending vertically to said N-type silicon layer, said second trench having a bottom surface that abuts said N-type channel region and is above and physically separated from said first P-type gate; and

filling said second trench with a semiconductor layer.

19. The method of claim 18, said filling of said second trench comprising filling said second trench with any one of a silicon layer, a second silicon germanium layer and a second silicon germanium carbide layer.

20. The method of claim 18, further comprising:

forming N-type source/drain regions for said junction field effect transistor, said forming of said N-type source/drain regions comprising forming N-type implant at a top surface of said substrate, said N-type implant regions being formed so as to abut said N-type channel region, so as to have a higher concentration of an N-type dopant than said N-type channel region and so that said second P-type gate is positioned laterally between said N-type implant regions; and

forming isolation structures so that said N-type source/drain regions are isolated from said second P-type gate.

21. The method of claim 18, further comprising:

forming a first contact extending vertically from said top surface to said first P-type gate; and

forming a second contact extending vertically from said top surface to said first N-well.

22. The method of claim 21, said first contact being formed so as to be electrically connected to said second P-type gate.