VERTICAL TRANSISTOR MANUFACTURING METHOD AND VERTICAL TRANSISTOR
First Claim
1. A method of manufacturing a vertical transistor comprising a substrate including a vertical stack of regions including a source region separated from a drain region by a channel region;
- forming a trench in said substrate, said trench at least partially extending into said vertical stack of regions;
lining said trench with a stack comprising a gate dielectric, an etch protection layer and a further insulating layer;
filling the remainder of the trench with a shield electrode material;
exposing a top portion of the shield electrode material by removing the further insulating layer to a first depth in said trench;
forming an inter electrode dielectric on the exposed shield electrode material;
removing the etch protection layer to the first depth from said trench; and
forming a gate electrode in said trench between the inter electrode dielectric and the exposed portion of the gate dielectric.
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Accused Products
Abstract
A method is disclosed of manufacturing a vertical transistor which comprises providing a substrate including a vertical stack of regions including a source region separated from a drain region by a channel region; forming a trench in said substrate, said trench at least partially extending into said vertical stack of regions; lining said trench with a stack comprising a gate dielectric liner, an etch protection layer and a further insulating layer; filling the remainder of the trench with a shield electrode material; exposing a top portion of the shield electrode material by removing the further insulating layer to a first depth in said trench; forming a inter electrode dielectric on the exposed shield electrode material; removing the etch protection layer to the first depth from said trench; and forming a gate electrode in said trench between the inter electrode dielectric liner and the exposed portion of the gate dielectric liner.
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Citations
15 Claims
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1. A method of manufacturing a vertical transistor comprising a substrate including a vertical stack of regions including a source region separated from a drain region by a channel region;
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forming a trench in said substrate, said trench at least partially extending into said vertical stack of regions; lining said trench with a stack comprising a gate dielectric, an etch protection layer and a further insulating layer; filling the remainder of the trench with a shield electrode material; exposing a top portion of the shield electrode material by removing the further insulating layer to a first depth in said trench; forming an inter electrode dielectric on the exposed shield electrode material; removing the etch protection layer to the first depth from said trench; and forming a gate electrode in said trench between the inter electrode dielectric and the exposed portion of the gate dielectric. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A vertical transistor comprising:
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a substrate including a vertical stack of regions including a source region separated from a drain region by a channel region and a trench lined with a gate dielectric, said trench at least partially extending through said vertical stack of regions, wherein said trench comprises a shield electrode and a gate electrode surrounding an upper portion of the shield electrode, and being laterally separated from the upper portion by an inter electrode dielectric covering said portion, and wherein the remainder of the shield electrode is laterally separated from the gate dielectric by a further insulating layer and an etch protection layer between the gate dielectric and the further insulating layer. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification