SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20120168881A1
• Filed: 01/27/2011
• Published: 07/05/2012
• Est. Priority Date: 12/29/2010
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Yin, Haizhou, Zhong, Huicai, Zhu, Huilong, Luo, Zhijiong
• Granted Patent: US 8,772,127 B2
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a silicon substrate having {100} crystal indices with a gate stack structure formed thereon;

forming an interlayer dielectric layer to cover a top surface of the silicon substrate;

forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, wherein the first trench has an extension direction being along <

110>

crystal direction and perpendicular to that of the gate stack structure; and

filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile-stressed dielectric layer.

2. The method for manufacturing a semiconductor device of claim 1, wherein the first dielectric layer is a tensile-stressed dielectric layer made of at least one of silicon nitride, silicon oxide and silicon oxynitride.

3. The method for manufacturing a semiconductor device of claim 1, wherein the first dielectric layer has a tensile stress of at least 1 GPa.

4. The method for manufacturing a semiconductor device of claim 1, wherein the gate stack structure comprises a gate electrode or a dummy gate electrode.

5. The method for manufacturing a semiconductor device of claim 4, wherein if the gate stack structure is a dummy gate electrode, the method further comprises:

performing an annealing process after the first dielectric layer is formed in order to memorize the tensile stress provided by the first dielectric layer in the silicon substrate.

6. The method for manufacturing a semiconductor device of claim 1, further comprising:

forming a second isolation region and a third isolation region in the silicon substrate, wherein the second isolation region has an extension direction parallel to that of the first trench, and the third isolation region has an extension direction perpendicular to that of the second isolation region, and wherein a MOS transistor comprising the gate stack structure is formed on the area of the silicon substrate surrounded by the second isolation region and the third isolation region, the second isolation region comprises a second dielectric layer, the third isolation region comprises a third dielectric layer, the first trench is formed above the second isolation region, and the second dielectric layer is exposed at bottom of the first trench.

7. The method for manufacturing a semiconductor device of claim 1, wherein the second dielectric layer is a tensile-stressed dielectric layer.

8. The method for manufacturing a semiconductor device of claim 7, wherein the second dielectric layer is a tensile-stressed dielectric layer made of at least one of silicon nitride, silicon oxide and silicon oxynitride.

9. The method for manufacturing a semiconductor device of claim 7, wherein the second dielectric layer has a tensile stress of at least 1 GPa.

10. The method for manufacturing a semiconductor device of claim 6, wherein the third dielectric layer is a low-stressed dielectric layer.

11. The method for manufacturing a semiconductor device of claim 10, wherein the third dielectric layer is a low-stressed dielectric layer made of at least one of silicon nitride, silicon oxide and silicon oxynitride.

12. The method for manufacturing a semiconductor device of claim 10, wherein the third dielectric layer has a stress of not more than 180 MPa.

13. The method for manufacturing a semiconductor device of claim 6, wherein after the first trench is formed, the second dielectric layer is exposed at the bottom of the first trench.

14. A semiconductor device, comprising:

a silicon substrate having {100} crystal indices;

a gate stack structure formed on the silicon substrate;

an interlayer dielectric layer covering a top surface of the silicon substrate; and

a first isolation region formed in the interlayer dielectric layer and/or in the gate stack structure, wherein the first isolation region has an extension direction being along <

110>

crystal direction and perpendicular to that of the gate stack structure, and the first isolation region comprises a first dielectric layer which is a tensile-stressed dielectric layer.

15. The semiconductor device of claim 14, wherein the first dielectric layer is a tensile-stressed dielectric layer made of at least one of silicon nitride, silicon oxide and silicon oxynitride.

16. The semiconductor device of claim 14, wherein the first dielectric layer has a tensile stress at least 1 GPa.

17. The semiconductor device of claim 14, wherein a second isolation region and a third isolation region are formed in the silicon substrate, wherein the second isolation region has an extension direction parallel to that of the first isolation region, and the third isolation region has an extension direction perpendicular to that of the second isolation region, and wherein a MOS transistor comprising the gate stack structure is formed on the area of the silicon substrate surrounded by the second isolation region and the third isolation region, the second isolation region comprises a second dielectric layer, the third isolation region comprises a third dielectric layer, the first isolation region is formed above the second isolation region, and the second dielectric layer is exposed at bottom of the first isolation region.

18. The semiconductor device of claim 17, wherein the second dielectric layer is a tensile-stressed dielectric layer.

19. The semiconductor device of claim 18, wherein the second dielectric layer is a tensile-stressed dielectric layer made of at least one of silicon nitride, silicon oxide and silicon oxynitride.

20. The semiconductor device of claim 18, wherein the second dielectric layer has a tensile stress of at least 1 GPa.

21. The semiconductor device of claim 17, wherein the third dielectric layer is a low-stressed dielectric layer.

22. The semiconductor device of claim 21, wherein the third dielectric layer is a low-stressed dielectric layer made of at least one of silicon nitride, silicon oxide and silicon oxynitride.

23. The semiconductor device of claim 21, wherein the third dielectric layer has a stress of not more than 180 MPa.

24. The semiconductor device of claim 17, wherein the first isolation region extends downwards into an upper portion of the second dielectric layer.