MULTI-LAYER DISTRIBUTED NETWORK

• US 20120169362A1
• Filed: 03/13/2012
• Published: 07/05/2012
• Est. Priority Date: 10/17/2008
• Status: Active Grant

• Current Assignee: Chooi Pei Lim, Keong Hong Oh, Siang Poh Lob, Yee Liang Tan
• Original Assignee: Chooi Pei Lim, Keong Hong Oh, Siang Poh Lob, Yee Liang Tan
• Inventors: Oh, Keong Hong, Tan, Yee Liang, Lim, Chooi Pei, Lob, Siang Poh
• Granted Patent: US 8,683,405 B2
• Time in Patent Office: Days
• US Class Current: 324/750.3
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/396 Clock trees

Abstract

Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

Claims

1. A test network in an integrated circuit, comprising:

a center network, wherein the center network branches into each quadrant of the integrated circuit; and

a quadrant network in each of the quadrants, wherein the quadrant networks are substantially identical and are each connected to the center network and wherein test signals are transmitted from test pins on the integrated circuit through the center network to each of the quadrant networks for testing of the integrated circuit.

2. The test network of claim 1, wherein each of the quadrant networks forms an H-tree structure.

3. The test network of claim 1, wherein the center network forms an H-tree structure and wherein the test network is contained within a base of the integrated circuit.

4. The test network of claim 1, further comprising:

pre-built buffers distributed along the test network, wherein there is at least one pre-built buffer in an evenly spaced area of around 400 μ

m×

400 μ

m across the integrated circuit.

5. The test network of claim 4, wherein the pre-built buffers can be detached from the test network when not used for testing the integrated circuit.

6. The test network of claim 1, wherein the test network functions as a clock network when not used for testing the integrated circuit.

7. A network in an integrated circuit prepared by a process, the process comprising:

creating the network;

placing buffers along the network in a predetermined manner, wherein each of the buffers is configurable to route a signal from the network to an associated logic cell; and

according to a design, connecting each of one or more of the buffers to a respective power terminal, wherein each of the one or more buffers electrically couples the respective power terminal to an associated logic cell.

8. The network in the integrated circuit of claim 7, wherein each extraneous buffer not used for testing the design is replaced with a tied off cell.

9. The network in the integrated circuit of claim 8, wherein the tied-off cells drives an output port of the integrated circuit directly from an internal power rail.

10. The network in the integrated circuit of claim 7, further comprising:

powering down each of the one or more buffers according to the design, wherein buffers not needed for testing the design are powered down to reduce current leakage.

11. The network in the integrated circuit of claim 7, wherein the signal comprises a test signal and the network is used to test the associated logic cells.

12. The network in the integrated circuit of claim 7, wherein the network comprises:

a center network branching into a plurality of quadrants in the integrated circuit, wherein the center network transmits test signals from test pins on the integrated circuit to each of the quadrants; and

a quadrant network in each of the quadrants, wherein each of the quadrant networks is connected to the center network to receive the transmitted test signals.