HIGH FREQUENCY PROBING STRUCTURE

• US 20120169367A1
• Filed: 12/30/2010
• Published: 07/05/2012
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Yung-Hsin, Hung, Wensen
• Granted Patent: US 8,878,560 B2
• Time in Patent Office: Days
• US Class Current: 324/756.03
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 1/06772 High frequency probes
• CPC Class Codes: G01R 1/07371 using an intermediate card or back card with apertures through which the probes pass
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49167 with deforming of conductive path

Abstract

The present disclosure provide a probe card for wafer level testing. The probe card includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch; a printed circuit board configured approximate the first surface of the space transformer; and a power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board.

20

Claims

1. A probe card for wafer level testing, comprising:

a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch;

a printed circuit board configured approximate the first surface of the space transformer; and

a power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board.

2. The probe card of claim 1, wherein the power plane includes copper foil.

3. The probe card of claim 1, further comprising solder balls configured to couple the signal lines of the space transformer to the printed circuit board.

4. The probe card of claim 1, further comprising an additional power plane disposed on the printed circuit board and patterned to couple with the power line and the ground line of the space transformer.

5. The probe card of claim 1, further comprising a high frequency matching circuit formed on the space transformer and coupled with the power line and ground line of the space transformer.

6. The probe card of claim 1, further comprising an interposer disposed between the space transformer and the printed circuit board, the interposer for coupling the power and ground lines of the space transformer to the printed circuit board.

7. The probe card of claim 6, further comprising a flexible membrane circuit having:

a first end disposed between the printed circuit board and the interposer; and

a second end disposed between the space transformer and the interposer.

8. The probe card of claim 6, further comprising a flexible membrane circuit having

a first end disposed between the space transformer and the interposer;

and

a second end formed on a top surface of the printed circuit board.

9. The probe card of claim 8, wherein the printed circuit board includes a through hole that the flexible membrane circuit passes through.

10. The probe card of claim 1, further comprising a plurality of needles configured to be aligned with bonding pads of multiple dies of a semiconductor wafer for multiple device testing in parallel.

11. A probe card for wafer level test, comprising:

a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes a first surface having a first pitch and a second surface having a second pitch substantially less than the first pitch;

a printed circuit board configured approximate the first surface of the space transformer;

a first power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line to the printed circuit board; and

a second power plane disposed on a surface of the printed circuit board and patterned to couple the power line and the ground line of the space transformer to the printed circuit board, wherein the second power plane is bonded with the first power plane.

12. The probe card of claim 11, further comprising solder balls configured to couple the signal lines of the space transformer to the printed circuit board.

13. The probe card of claim 11, further comprising an interposer disposed between the space transformer and the printed circuit board, the interposer for coupling the power and ground lines of the space transformer to the printed circuit board.

14. The probe card of claim 13, further comprising a flexible membrane circuit having:

a first end disposed between the printed circuit board and the interposer; and

a second end disposed between the space transformer and the interposer.

15. A wafer test system, comprising:

a probe card designed to test a wafer including;

a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch,

a printed circuit board configured approximate the first surface of the space transformer, and

a first power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line to the printed circuit board;

a wafer prober designed to hold a wafer to be tested and control the probe card during a wafer test; and

a tester coupled to the probe card through a connection cable.

16. The wafer test system of claim 15, wherein the probe card further includes a second power plane formed on the printed circuit board and coupled with the first power plane.

17. The wafer test system of claim 15, wherein the probe card further comprises a high frequency matching circuit formed on the space transformer and coupled with the power line and ground line of the space transformer.

18. The wafer test system of claim 15, wherein the probe card further comprises an interposer disposed between the space transformer and the printed circuit board, the interposer for coupling the power and ground lines of the space transformer to the printed circuit board.

19. The wafer test system of claim 18, wherein the probe card further includes a flexible membrane circuit having:

a first end disposed between the printed circuit board and the interposer; and

a second end disposed between the space transformer and the interposer.

20. The wafer test system of claim 18, wherein the probe card further includes a flexible membrane circuit having:

a first end disposed between the space transformer and the interposer; and

a second end formed on a top surface of the printed circuit board.