GLITCH FREE CLOCK SWITCHING CIRCUIT

• US 20120169373A1
• Filed: 01/05/2011
• Published: 07/05/2012
• Est. Priority Date: 01/05/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: LANGADI, SAYA GOUD
• Granted Patent: US 8,384,435 B2
• Time in Patent Office: Days
• US Class Current: 326/93
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03K 5/19 Monitoring patterns of pulse trains indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02

Abstract

A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output.

Claims

1. A clock switching circuit that provides a clock output selectable from a plurality of clock signals, the clock switching circuit comprising:

a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic, the first enable synchronization logic configured to receive a first clock signal;

a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic, the second enable synchronization logic configured to receive a second clock signal;

a logic gate that receives the second enable and the second clock signal, the logic gate coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high;

a priority multiplexer that receives the first clock signal, the first enable and the logic gate output, the multiplexer configured to select the first clock signal as the clock output if the first enable is a logic high, irrespective of the logic gate output.

2. The clock switching circuit of claim 1, wherein at least the first clock signal and the second clock signal of the plurality of clock signals are asynchronous clock signals.

3. The clock switching circuit of claim 1, wherein the first enable synchronization logic comprises a first plurality of negative edge flip flops that are coupled to each other and the second enable synchronization logic comprises a second plurality of negative edge flip-flops that are coupled to each other.

4. The clock switching circuit of claim 3, wherein

the first plurality of negative edge flip flops receives the first enable and generates the first clock enable;

and

wherein the second plurality of negative edge flip flops receives the second enable and generates the second clock enable.

5. The clock switching circuit of claim 1, wherein the first enable generation logic generates the first enable in response to a first clock select and the second clock enable;

and wherein the second enable generation logic generates the second enable in response to a second clock select and the second clock enable.

6. The clock switching circuit of claim 1, wherein the plurality of negative edge flip flops receives a RESET signal at power up of the clock switching circuit.

7. The clock switching circuit of claim 1, wherein the first clock signal is a default clock signal.

8. The clock switching circuit of claim 7, wherein the first enable is logic high at reset.

9. The clock switching circuit of claim 1, wherein the priority multiplexer is configured to block a glitch at the logic gate output.

10. The clock switching circuit of claim 1, wherein the logic gate includes an AND gate.

11. A clock switching circuit comprising:

a first clock domain comprising a first enable generation logic coupled to a first enable synchronization logic;

the first enable synchronization logic that generates a first clock enable in response to an input from the first enable generation logic;

the first clock domain further comprising a first logic gate that receives a first clock signal and outputs the first clock signal as a first clock output according to the first clock enable;

a second clock domain comprising a second enable generation logic coupled to a second enable synchronization logic;

the second enable synchronization logic that generates a second clock enable in response to an input from the second enable generation logic, the second clock domain further comprising a second logic gate that receives a second clock signal and outputs the second clock signal as a second clock output according to the second clock enable;

a first feedback path from first clock domain to the second clock domain;

a second feedback path from the second clock domain to the first clock domain; and

a missing clock detection circuit that detects absence of the second clock signal, wherein if the second clock signal is missing, the missing clock detection circuit sends a CLK OFF signal to the second enable synchronization logic that breaks the second feedback path such that an output of the clock switching circuit is switched from the second clock signal to the first clock signal in response to the CLK OFF signal.

12. The clock switching circuit of claim 11, wherein the first enable generation logic generates the first enable in response to a first clock select and the second clock enable;

and wherein the second enable generation logic generates the second enable in response to a second clock select and the second clock enable.

13. The clock switching circuit of claim 12, wherein the first clock select is logic high in response to CLK OFF signal such that the second clock enable is logic low, asynchronously.

14. The clock switching circuit of claim 11, wherein the CLK OFF signal includes a memory mapped bit.

15. The clock switching circuit of claim 14, wherein the memory mapped bit is modified by a processor coupled to the clock switching circuit.

16. The clock switching circuit of claim 11 comprises an application specific integrated circuit.

17. A clock switching circuit comprising:

a first enable generation logic configured to receive a first clock select signal and a second clock enable, the first enable generation logic having an output that is coupled to a first enable synchronization logic;

the first enable synchronizer logic configured to generate a first clock enable in response to receiving a RESET signal and a first CLK OFF signal, the first CLK OFF signal indicative of the absence of a first clock signal;

a second enable generation logic configured to receive a second clock select signal and the first clock enable, the second enable generation logic having an output that is coupled to a second enable synchronization logic;

the second enable synchronizer logic configured to generate a second clock enable in response to receiving the RESET signal and a second CLK OFF signal, the first CLK OFF signal being indicative of the absence of a first clock signal;

a logic gate coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high;

a priority multiplexer that receives the first clock signal, the first enable and the logic gate output, the multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output; and

a missing clock detection circuit that detects absence of at least one of the first clock signal and the second clock signal and that generates the first CLK OFF signal and the second CLK OFF signal respectively.

18. The clock switching circuit of claim 17, wherein the first enable synchronization logic comprises a first plurality of negative edge flip flops that are coupled to each other and the second enable synchronization logic comprises a second plurality of negative edge flip-flops that are coupled to each other.