DIGITAL SIGNAL FILTER

• US 20120169433A1
• Filed: 02/09/2011
• Published: 07/05/2012
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Johnson, Timothy M., Mullins, Scott P., Perez, Yehonatan
• Granted Patent: US 8,565,709 B2
• Time in Patent Office: Days
• US Class Current: 333/181
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H03H 7/1758 Series LC in shunt or branch path H03H7/1791 takes precedence

Abstract

A passive filter circuit filters an input signal to attenuate an undesired frequency. The passive filter circuit includes a first stage and a second stage. The input to the first stage is the input signal. The first stage includes a first inductor and a first branch coupled to the output of the first inductor. The first branch includes a first capacitor and a second inductor. The first stage is coupled to the second stage. The second stage includes a third inductor and a second branch coupled to the output of the third inductor. The second branch includes a second capacitor. Other embodiments are also described and claimed.

Claims

1. A passive filter circuit for filtering an input signal to attenuate an undesired frequency, comprising:

a first stage to receive the input signal, the first stage having a first inductor and a first branch coupled to the output of the first inductor, the first branch having a first capacitor and a second inductor; and

a second stage coupled to the first stage, the second stage having a third inductor and a second branch coupled to the output of the third inductor, the second branch having a second capacitor.

2. The passive filter circuit of claim 1, wherein the undesired frequency is a radio communications frequency.

3. The passive filter circuit of claim 2, wherein the radio communications frequency is between 800 MHz and 900 MHz.

4. The passive filter circuit of claim 1, wherein a capacitance value of the first capacitor substantially equals a capacitance value of the second capacitor.

5. The passive filter circuit of claim 1, wherein the first capacitor and the second inductor are discrete components, wherein addition of the second inductor to the first branch lowers a resonant frequency of the first branch without having to increase a capacitance value of the first capacitor, which degrades a rise time of an output signal.

6. The passive filter circuit of claim 5, wherein the rise time of the output signal does not exceed 12 nanoseconds.

7. The passive filter circuit of claim 1, wherein the inductance value of the second inductor is smaller than that of the first inductor and the third inductor.

8. The passive filter circuit of claim 1, wherein the second branch provides a rolled-off frequency response at frequencies above the undesired frequency.

9. A passive filter circuit for filtering a digital signal to attenuate an undesired frequency, comprising:

an input terminal to receive a digital signal;

an output terminal to provide a filtered version of the digital signal;

a first inductor, a second inductor, and a third inductor, the first inductor and the third inductor coupled in series between the input terminal and the output terminal; and

a first capacitor and a second capacitor, the first capacitor and the second inductor coupled in series between (1) a node that is between the first inductor and the third inductor and (2) ground, wherein the second capacitor is coupled between the output terminal and ground.

10. The passive filter circuit of claim 9, wherein the inductance and capacitance values of the first inductor, the first capacitor, and the second inductor are selected to attenuate the undesired frequency, the undesired frequency being a radio communications frequency.

11. The passive filter circuit of claim 10, wherein the radio communications frequency is between 800 MHz and 900 MHz and the digital signal'"'"'s fundamental frequency is less than 100 MHz.

12. The passive filter circuit of claim 9, wherein a capacitance value of the first capacitor substantially equals a capacitance value of the second capacitor.

13. The passive filter circuit of claim 9, wherein the inductance value of the second inductor is smaller than that of the first inductor and the third inductor.

14. The passive filter circuit of claim 9, wherein the second inductor lowers a resonant frequency of the passive filter circuit without having to increase a capacitance value of the first capacitor, which degrades a rise time of the filtered version of the digital signal.

15. The passive filter circuit of claim 14, wherein the rise time of the filtered version of the digital signal does not exceed 12 nanoseconds.

16. The passive filter circuit of claim 9, wherein the second capacitor connected between the output terminal and ground provides a rolled-off frequency response at frequencies above the undesired frequency.

17. A mobile communications device, comprising:

an antenna coupled to radio communications circuitry to establish a wireless connection through a wireless communications network;

camera circuitry to capture an image of a scene;

a clock signal generator to produce a clock signal for operation of the camera circuitry; and

a passive filter circuit having an input coupled to the clock signal generator, an output coupled to the camera circuitry, a first inductor at the input, a pi filter coupled to the first inductor, the pi filter having a first leg with a first capacitor and a second leg with a second capacitor, and a second inductor coupled in series with the first capacitor in the first leg of the pi filter.

18. The mobile communications device of claim 17, wherein a capacitance value of the first capacitor substantially equals a capacitance value of the second capacitor.

19. The mobile communications device of claim 17, wherein the inductance value of the second inductor is smaller than that of the first inductor and the third inductor.

20. The mobile communications device of claim 17, wherein the passive filter circuit is designed to attenuate an undesired frequency between 800 MHz and 900 MHz.

21. The mobile communications device of claim 20, wherein the second leg provides a rolled-off frequency response at frequencies above the undesired frequency.

22. The mobile communications device of claim 17, wherein the second inductor lowers the resonant frequency of the first leg without having to increase a capacitance value of the first capacitor, which degrades a rise time of an output signal of the passive filter circuit.

23. The mobile communications device of claim 22, wherein the rise time of the output signal does not exceed 12 nanoseconds.