Gate driving circuit and display device including the same

• US 20120169709A1
• Filed: 09/23/2011
• Published: 07/05/2012
• Est. Priority Date: 12/31/2010
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Lee, Seung Kyu, Lee, Dong-Hoon, Yoon, Joo-Sun, Park, Jinwoo, Yang, Jinwook, Park, Sangjin
• Application Number:
  US13/200,397
• Publication Number:
  US 20120169709A1
• Time in Patent Office: Days
• US Class Current: 345/215
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A gate driving circuit includes a pre-charge unit, a pull-up unit, a first capacitor, and a discharge unit. The pre-charge unit pre-charges a first node in response to a first input signal. The pull-up unit outputs a gate driving signal for driving a gate line to a first clock signal in response to a signal at the first node. The first capacitor is connected between the first node and a first voltage. The discharge unit discharges the first node in response to a second input signal and a second clock signal.

Claims

1. A gate driving circuit, comprising:

a pre-charge unit pre-charging a first node in response to a first input signal;

a pull-up unit outputting a gate driving signal for driving a gate line to a first clock signal in response to a signal at the first node;

a first capacitor connected between the first node and a first voltage; and

a discharge unit discharging the first node in response to a second input signal and a second clock signal.

2. The gate driving circuit of claim 1, wherein the first capacitor comprises an active-to-metal capacitor, wherein an active terminal of the active-to-metal capacitor is connected to the first node and a metal terminal of the active-to-metal capacitor is connected to the first voltage.

3. The gate driving circuit of claim 2, wherein:

when the active terminal of the active-to-metal capacitor is an n type active terminal, the first voltage is set to have a voltage level between a ground voltage and a first operation voltage, and

when the active terminal of the active-to-metal capacitor is a p type active terminal, the first voltage is set to have a voltage level between the ground voltage and a second operation voltage.

4. The gate driving circuit of claim 3, wherein the pre-charge unit comprises:

a first transistor connected between a second voltage and a second node, the first transistor having a gate controlled by a first input signal; and

a second transistor connected between the second voltage and the first node, the second transistor having a gate controlled by the first input signal.

5. The gate driving circuit of claim 4, wherein the pull-up unit comprises a third transistor connected between the first clock signal and the gate line, the third transistor having a gate connected to the first node.

6. The gate driving circuit of claim 5, further comprising a fourth transistor connected between the gate line and the second node, the fourth transistor having a gate controlled by a signal of the gate line.

7. The gate driving circuit of claim 6, wherein the discharge unit comprises:

a fifth transistor connected between the second node and a third voltage, the fifth transistor having a gate controlled by a second input signal;

a sixth transistor connected between the second node and the second operation voltage, the sixth transistor having a gate connected to a third node;

a seventh transistor connected between the second node and the first node, the seventh transistor having a gate connected to the third node;

an eighth transistor connected between the second node and the first node, the eighth transistor having a gate controlled by the second input signal;

a second capacitor connected between the first clock signal and the third node;

a ninth transistor connected between the third node and the second operation voltage, the ninth transistor having a gate connected to the first node;

a tenth transistor connected between the gate line and the second operation voltage, the tenth transistor having a gate connected to the third node; and

an eleventh transistor connected between the gate line and the second operation voltage, the eleventh transistor having a gate connected the second clock signal.

8. The gate driving circuit of claim 3, wherein the pre-charge unit comprises:

a first transistor connected between the first input signal and a fourth node, the first transistor having a gate connected to a second voltage;

a second transistor connected between the second input signal and the fourth node, the second transistor having a gate connected to a third voltage; and

third and fourth transistors sequentially connected between the fourth node and the first node in series, the third and fourth transistors respectively having gates connected to the second clock signal.

9. The gate driving circuit of claim 8, wherein the pull-up unit comprises fifth and sixth transistors sequentially connected between the first clock signal and the gate line in series, the fifth and sixth transistors respectively having gates connected to the first node.

10. The gate driving circuit of claim 9, wherein the discharge unit comprises:

seventh and eighth transistors sequentially connected between the third voltage and a fifth node in series, the seventh and eighth transistors respectively having gates connected to the first input signal;

ninth and tenth transistors sequentially connected between the second voltage and the fifth node in series, the ninth and tenth transistors respectively having gates connected to the second input signal;

eleventh and twelfth transistors sequentially connected between the first node and the second operation voltage in series, the eleventh and twelfth transistors respectively having gates connected to the fifth node;

a twelfth transistor connected between the second operation voltage and the fifth node, the twelfth transistor having a gate connected to a control signal;

a second capacitor connected between the fifth node and the second operation voltage; and

a fourteenth transistor connected between the gate line and the second operation voltage, the fourteenth transistor having a gate connected to the fifth node.

11. A display device, comprising:

a display panel comprising a plurality of gate lines, a plurality of source lines perpendicularly intersecting the gate lines, and a plurality of pixels respectively formed at intersection points of the gate lines and source lines;

a first gate driving circuit driving gate lines of a first group of gate lines from among the plurality of gate lines, the first gate driving circuit including a plurality of first stages dependently connected thereto; and

a second gate driving circuit driving gate lines of a second group of gate lines from among the plurality of gate lines, the second gate driving circuit including a plurality of second stages dependently connected thereto,

wherein each stage of the first and second stages includes;

a pre-charge unit pre-charging a first node in response to a first input signal;

a pull-up unit outputting a gate driving signal for driving a gate line to a first clock signal in response to a signal at the first node;

a first capacitor connected between the first node and a first voltage; and

a discharge unit discharging the first node in response to a second input signal and a second clock signal.

12. The display device of claim 11, wherein:

the first group of gate lines is odd-numbered gate lines, and

the second group of gate lines is even-numbered gate lines.

13. The gate driving circuit of claim 12, wherein the first capacitor comprises an active-to-metal capacitor, wherein an active terminal of the active-to-metal capacitor is connected to the first node and a metal terminal of the active-to-metal capacitor is connected to the first voltage.

14. The gate driving circuit of claim 13, wherein:

the first voltage is set to have a voltage level between a ground voltage and a first operation voltage when the active terminal of the active-to-metal capacitor has an n type active terminal, and

the first voltage is set to have a voltage level between the ground voltage and a second operation voltage when the active terminal of the active-to-metal capacitor has a p type active terminal.