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MEMORY DEVICE, DISPLAY DEVICE EQUIPPED WITH MEMORY DEVICE, DRIVE METHOD FOR MEMORY DEVICE, AND DRIVE METHOD FOR DISPLAY DEVICE

  • US 20120169753A1
  • Filed: 04/23/2010
  • Published: 07/05/2012
  • Est. Priority Date: 09/16/2009
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • a memory array in which memory cells are provided in a matrix pattern;

    a row driver which drives each row of the memory array;

    a column driver which drives each column of the memory array;

    a first wire which is provided for the each row and connects memory cells in an identical row;

    a second wire and a third wire each of which connects the memory cells; and

    a fourth wire which is provided for the each column and connects memory cells in an identical column, the fourth wire being driven by the column driver so that each of a first electric potential level and a second electric potential level each indicating a binary logic level is supplied to the fourth wire,the memory cells of the memory array each including;

    a switching circuit;

    a first retaining section;

    a transfer section;

    a second retaining section; and

    a first control section,the switching circuit being driven by the row driver via the first wire, so as to selectively turn on/off between the fourth wire and the first retaining section,the first retaining section retaining the binary logic level to be supplied thereto,the transfer section being driven via the second wire, so as to selectively carry out (i) a transfer operation in which the binary logic level retained in the first retaining section is transferred to the second retaining section in a state in which the binary logic level remains retained in the first retaining section and (ii) a non-transfer operation in which no transfer operation is carried out,the second retaining section retaining the binary logic level to be supplied thereto,the first control section being driven via the third wire, so as to be selectively controlled to be in a state in which the first control section carries out a first operation or a second operation,the first operation being an operation which is carried out by the first control section in (i) an active state in which the first control section receives an input thereto and supplies the input as an output thereof to the first retaining section or (ii) a non-active state in which the first control section stops carrying out an output, the active or non-active state having been selected in accordance with control information indicative of which of the first electric potential level and the second electric potential level is retained in the second retaining section as the binary logic level,the second operation being an operation in which the first control section stops carrying out the output regardless of the control information, andsaid memory device further comprising a voltage supply which supplies a set electric potential to an input of the first control section.

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