SEMICONDUCTOR DEVICE AND METHOD OF GENERATING VOLTAGES USING THE SAME

• US 20120170367A1
• Filed: 12/28/2011
• Published: 07/05/2012
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KOO, Bon Kwang
• Granted Patent: US 8,879,316 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A semiconductor device includes a register unit for storing additional bits associated with a command signal and outputting a selected additional bit corresponding to a received address; a combination circuit for combining received control bits and the selected additional bit, and outputting enable signals based on the combined bits, where the received control bits are generated in response to the command signal and a control signal; and a voltage generation circuit for outputting voltages distributed in response to the enable signals.

Claims

1. A semiconductor device, comprising:

a register unit for storing additional bits associated with a command signal and outputting a selected additional bit corresponding to a received address among the additional bits;

a combination circuit for combining received control bits and the selected additional bit, and outputting enable signals based on the combined bits, where the received control bits are generated in response to the command signal and a control signal; and

a voltage generation circuit for outputting voltages distributed in response to the enable signals.

2. The semiconductor device of claim 1, further comprising a control bit generator for generating the control bits wherein the control bit generator serially outputs the control bits 8 bits in response to the command signal and the control signal.

3. The semiconductor device of claim 1, wherein the register unit comprises registers each of which stores 1 byte of data.

4. The semiconductor device of claim 3, wherein the registers comprise:

a register for storing the additional bits for a program operation;

a register for storing the additional bits for a read operation; and

a register for storing the additional bits for an erase operation.

5. The semiconductor device of claim 3, wherein the registers store the additional bits for a program, a read, and an erase operation.

6. The semiconductor device of claim 3, wherein each of the registers comprises eight depositories for storing data of 8 bits.

7. The semiconductor device of claim 6, wherein the received address is assigned to each of the registers and each of the depositories.

8. The semiconductor device of claim 1, wherein the voltage generation circuit comprises:

a voltage generator for generating a reference voltage;

a voltage distributor for generating distributed voltages of various levels based on the reference voltage and a feedback voltage; and

a switch circuit for outputting the distributed voltage as voltage for a relevant operation in response to the enable signals.

9. The semiconductor device of claim 8, wherein the voltage distributor comprises:

a comparator for outputting the distributed voltages to an output terminal in response to the reference voltage and the feedback voltage; and

a plurality of resistors coupled in series between the output terminal and a ground terminal.

10. The semiconductor device of claim 9, wherein the feedback voltage is supplied to a node between two resistors placed in a middle of the resistors.

11. The semiconductor device of claim 9, wherein the switch circuit comprises a plurality of switches each coupled between the resistors of the distributor and configured to share the output terminal.

12. The semiconductor device of claim 11, wherein the plurality of switches are implemented using respective NMOS transistors operated in response to respective enable signals.

13. The semiconductor device of claim 11, wherein the switches are turned on in response to respective enable signals and each configured to transfer the voltage, distributed into the node between relevant resistors of the resistors, to the output terminal.

14. A method of generating voltages, comprising:

generating control bits in response to a command signal;

outputting a selected additional bit selected based on an address, from among additional bits associated with the command signal;

combining the control bits and the selected additional bit to arrive at combined bits;

outputting enable signals based on the combined bits; and

outputting distributed voltages in response to the enable signals.

15. The method of claim 14, wherein the control bits are any one of 00000000 to 11111111.

16. The method of claim 14, wherein the selected additional bit is 0 or 1.

17. The method of claim 16, wherein if the selected additional bit is 0, the enable signals are outputted based on the control bits.

18. The method of claim 16, wherein if the selected additional bit is 1, the control bits and the additional bit of 1 are combined and the enable signals are outputted based on the combined bits.

19. A semiconductor device, comprising:

a register unit for storing additional bits associated with a command signal and outputting a selected additional bit corresponding to a received address among the additional bits; and

a combination circuit for combining received control bits and the selected additional bit, and outputting enable signals based on the combined bits, where the received control bits are generated in response to the command signal and a control signal, and where the enable signals are associated with a voltage to be outputted.

20. The semiconductor device of claim 19, wherein the register unit comprises registers each of which stores 1 byte of data, where the registers further comprise:

a register for storing the additional bits for a program operation;

a register for storing the additional bits for a read operation; and

a register for storing the additional bits for an erase operation.