DECOUPLING SAMPLING CLOCK AND ERROR CLOCK IN A DATA EYE
First Claim
1. An apparatus comprising:
- an eye monitor configured to generate a data eye from a data stream subject to equalization, the eye monitor including at least one error sampler, at least one transition sampler, and at least one data sampler;
a clock and data recovery (CDR) circuit configured to generate a transition clock for each transition sampler based on data transitions in the data eye, wherein the CDR shifts, in phase, the transition clock with a fixed phase offset to generate an error clock signal to each error sampler and, at an initial time, a data clock to each data sampler, andan adaptation module configured to adaptively set parameters of equalization applied to the data stream based upon an output of the error sampler and an output of the data sampler,wherein, at a subsequent time, the CDR decouples the error clock and the data clock to generate a relative optimum phase for the decoupled data clock for each data sampler.
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Accused Products
Abstract
In described embodiments, a transceiver includes an eye monitor, clock and data recovery, and adaptation modules. Data sampling clock phase and error clock phase determined from a data eye are decoupled in the transceiver during a sampling phase correction process. Decoupling these clock phases during the sampling phase correction process allows relative optimization of system equalization parameters without degradation of various adaptation algorithms. Such adaptation algorithms might be employed for received signal gain and equalization such as, for example, Decision Feedback Equalizer (DFE) adaptation. Deriving the data sampling clock and error clock phases from the same clock generation source and with independent clock control enables an iterative sampling phase correction process that allows for accelerated clock and data recovery (CDR) without disturbing the data eye shape.
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Citations
20 Claims
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1. An apparatus comprising:
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an eye monitor configured to generate a data eye from a data stream subject to equalization, the eye monitor including at least one error sampler, at least one transition sampler, and at least one data sampler; a clock and data recovery (CDR) circuit configured to generate a transition clock for each transition sampler based on data transitions in the data eye, wherein the CDR shifts, in phase, the transition clock with a fixed phase offset to generate an error clock signal to each error sampler and, at an initial time, a data clock to each data sampler, and an adaptation module configured to adaptively set parameters of equalization applied to the data stream based upon an output of the error sampler and an output of the data sampler, wherein, at a subsequent time, the CDR decouples the error clock and the data clock to generate a relative optimum phase for the decoupled data clock for each data sampler. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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generating, with an eye monitor, a data eye from a data stream subject to equalization, the eye monitor including at last one error sampler, at least one transition sampler, and at least one data sampler; generating, with a clock and data recovery (CDR) circuit, a transition clock for each transition sampler based on data transitions in the data eye; shifting, in phase, the transition clock with a fixed phase offset, thereby generating an error clock signal to each error sampler and, at an initial time, a data clock to each data sampler; adaptively setting parameters of equalization applied to the data stream based upon an output of the error sampler and an output of the data sampler; decoupling, by the CDR circuit, the error clock and the data clock; and generating, at a subsequent time, a relative optimum phase for the decoupled data clock for each data sampler. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for adaptively setting equalization in a receiver, comprising the steps of:
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generating, with an eye monitor, a data eye from a data stream subject to equalization, the eye monitor including at last one error sampler, at least one transition sampler, and at least one data sampler; generating, with a clock and data recovery (CDR) circuit, a transition clock for each transition sampler based on data transitions in the data eye; shifting, in phase, the transition clock with a fixed phase offset, thereby generating an error clock signal to each error sampler and, at an initial time, a data clock to each data sampler; adaptively setting parameters of equalization applied to the data stream based upon an output of the error sampler and an output of the data sampler; decoupling, by the CDR circuit, the error clock and the data clock; and generating, at a subsequent time, a relative optimum phase for the decoupled data clock for each data sampler.
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Specification