AUTO CONFIGURABLE 2/3 WIRE SERIAL INTERFACE

• US 20120170690A1
• Filed: 06/29/2011
• Published: 07/05/2012
• Est. Priority Date: 04/19/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Ngo, Christopher Truong, Arkiszewski, Roman Zbigniew, Hunkele, Brad
• Granted Patent: US 8,983,409 B2
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 2200/171 A filter circuit coupled to the output of an amplifier
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/27 A biasing circuit node being switched in an amplifier circuit
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/414 A switch being coupled in the output circuit of an amplifier to switch the output on/off
• CPC Class Codes: H03F 2200/417 A switch coupled in the output circuit of an amplifier being controlled by a circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/504 the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier
• CPC Class Codes: H03F 2200/534 Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/537 A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2203/21106 An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
• CPC Class Codes: H03F 2203/21142 Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 2203/21157 A filter circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 : with semiconductor devices only
• CPC Class Codes: H03F 3/602 : Combinations of several amplifiers
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

An automatically configurable 2-wire/3-wire serial communications interface (AC23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. The SOS detection circuitry provides an indication of detection of the SOS to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS. As such, the AC23SCI automatically configures itself for operation with some 2-wire and some 3-wire serial communications buses without external intervention.

Claims

1. Circuitry comprising:

sequence processing circuitry adapted to initiate processing of a received sequence based on a start-of-sequence (SOS) detection signal; and

SOS detection circuitry adapted to;

when coupled to a 2-wire serial communications bus, detect an SOS based on a serial data signal and a serial clock signal;

when coupled to a 3-wire serial communications bus, detect an SOS based on a chip select (CS) signal; and

in response to detecting the SOS, provide the SOS detection signal to the sequence processing circuitry.

2. The circuitry of claim 1 wherein:

when coupled to the 2-wire serial communications bus, the SOS detection circuitry is further adapted to receive the serial data signal and the serial clock signal via the 2-wire serial communications bus;

when coupled to the 3-wire serial communications bus, the SOS detection circuitry is further adapted to receive the serial data signal, the serial clock signal, and the CS signal via the 3-wire serial communications bus; and

the sequence processing circuitry is further adapted to initiate the processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS.

3. The circuitry of claim 1 wherein:

the SOS detection circuitry has a CS input;

the SOS detection circuitry comprises a CS resistive element coupled to the CS input; and

when the SOS detection circuitry is coupled to the 3-wire serial communications bus, the CS input is adapted to receive the CS signal.

4. The circuitry of claim 3 wherein the CS resistive element is coupled between the CS input and a ground.

5. The circuitry of claim 1 further comprising control circuitry, wherein:

the control circuitry is coupled to the SOS detection circuitry via the 2-wire serial communications bus;

the control circuitry is adapted to provide the serial clock signal; and

the control circuitry is adapted to provide the serial data signal.

6. The circuitry of claim 1 further comprising control circuitry, wherein:

the control circuitry is coupled to the SOS detection circuitry via the 3-wire serial communications bus;

the control circuitry is adapted to provide the serial clock signal;

the control circuitry is adapted to provide the serial data signal; and

the control circuitry is adapted to provide the CS signal.

7. The circuitry of claim 1 wherein when the SOS detection circuitry is coupled to the 3-wire serial communications bus, the SOS detection circuitry is further adapted to detect the SOS based on a LOW to HIGH transition of the CS signal.

8. The circuitry of claim 1 wherein when the SOS detection circuitry is coupled to the 3-wire serial communications bus, the SOS detection circuitry is further adapted to detect the SOS based on a HIGH to LOW transition of the CS signal.

9. The circuitry of claim 1 wherein the SOS detection circuitry is further adapted to detect the SOS based on a pulse of the serial data signal, such that during the pulse of the serial data signal, the serial clock signal does not transition.

10. The circuitry of claim 9 wherein during the received sequence, the serial data signal has a data bit period, which is about equal to a duration of the pulse of the serial data signal.

11. The circuitry of claim 10 wherein during the received sequence, the serial clock signal has a serial clock period, which is about equal to the data bit period.

12. The circuitry of claim 1 wherein when the SOS detection circuitry is coupled to the 3-wire serial communications bus, the SOS detection circuitry is further adapted to:

receive the serial data signal and receive the serial clock signal via the 3-wire serial communications bus; and

detect an SOS based on the serial data signal and the serial clock signal.

13. The circuitry of claim 1 wherein the SOS detection circuitry and the sequence processing circuitry provide a first automatically configurable 2-wire/3-wire serial communications interface (AC23SCI).

14. The circuitry of claim 13 wherein the first AC23SCI is a mobile industry processor interface.

15. The circuitry of claim 14 wherein the first AC23SCI is a radio frequency (RF) front-end (FE) interface.

16. The circuitry of claim 13 wherein the first AC23SCI is a slave device.

17. The circuitry of claim 13 further comprising:

a first radio frequency (RF) power amplifier (PA) comprising a first final stage having a first final bias input, such that bias of the first final stage is via the first final bias input;

PA control circuitry;

a PA-digital communications interface (DCI) coupled between a digital communications bus and the PA control circuitry; and

a final stage current digital-to-analog converter (IDAC) coupled between the PA control circuitry and the first final bias input.

18. The circuitry of claim 17 wherein the first AC23SCI is the PA-DCI.

19. The circuitry of claim 13 further comprising:

a first radio frequency (RF) power amplifier (PA) having a first final stage and adapted to;

receive and amplify a first RF input signal to provide a first RF output signal; and

receive a first final bias signal to bias the first final stage;

PA bias circuitry adapted to receive a bias power supply signal and provide the first final bias signal based on the bias power supply signal; and

a direct current (DC)-DC converter adapted to receive a DC power supply signal from a DC power supply and provide the bias power supply signal based on the DC power supply signal, such that a voltage of the bias power supply signal is greater than a voltage of the DC power supply signal.

20. The circuitry of claim 13 further comprising:

a direct current (DC)-DC converter comprising;

a power amplifier (PA) envelope power supply comprising a charge pump buck converter coupled to radio frequency (RF) PA circuitry; and

a PA bias power supply comprising a charge pump coupled to the RF PA circuitry; and

the RF PA circuitry.

21. The circuitry of claim 20 further comprising a second AC23SCI wherein:

the RF PA circuitry comprises a PA-digital communications interface (DCI) coupled to a digital communications bus, such that the first AC23SCI is the PA-DCI; and

the DC-DC converter further comprises a DC-DC converter DCI coupled to the digital communications bus, such that the second AC23SCI is the DC-DC converter DCI.

22. The circuitry of claim 13 further comprising:

multi-mode multi-band radio frequency (RF) power amplification circuitry having at least a first RF input and a plurality of RF outputs, such that;

configuration of the multi-mode multi-band RF power amplification circuitry associates one of the at least the first RF input with one of the plurality of RF outputs; and

the configuration is associated with configuration information;

power amplifier (PA) control circuitry coupled between the multi-mode multi-band RF power amplification circuitry and a PA-digital communications interface (DCI), such that the PA control circuitry has at least a first look-up table (LUT), which provides the configuration information defined by at least a first defined parameter set; and

the PA-DCI, which is coupled to a digital communications bus.

23. The circuitry of claim 22 wherein the first AC23SCI is the PA-DCI.

24. The circuitry of claim 1 further comprising:

a first radio frequency (RF) power amplifier (PA) comprising;

a first non-quadrature PA path having a first single-ended output; and

a first quadrature PA path coupled between the first non-quadrature PA path and an antenna port, such that the first quadrature PA path has a first single-ended input, which is coupled to the first single-ended output; and

a second RF PA comprising a second quadrature PA path coupled to the antenna port,

wherein the antenna port is configured to be coupled to an antenna.

25. The circuitry of claim 1 further comprising:

a first multi-mode multi-band quadrature radio frequency (RF) power amplifier (PA) coupled to multi-mode multi-band alpha switching circuitry via a single alpha PA output; and

the multi-mode multi-band alpha switching circuitry having;

a first alpha non-linear mode output associated with a first non-linear mode RF communications band; and

a plurality of alpha linear mode outputs, such that each of the plurality of alpha linear mode outputs is associated with a corresponding one of a first plurality of linear mode RF communications bands.

26. A method comprising:

providing sequence processing circuitry and start-of-sequence (SOS) detection circuitry;

initiating processing of a received sequence based on an SOS detection signal;

when coupled to a 2-wire serial communications bus, detecting an SOS based on a serial data signal and a serial clock signal;

when coupled to a 3-wire serial communications bus, detecting an SOS based on a chip select (CS) signal;

in response to detecting the SOS, providing the SOS detection signal.