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METHOD AND SYSTEM FOR SYSTEMATIC DEFECT IDENTIFICATION

  • US 20120170830A1
  • Filed: 12/29/2010
  • Published: 07/05/2012
  • Est. Priority Date: 06/14/2010
  • Status: Active Grant
First Claim
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1. A method for identifying a suspect layout feature from a plurality of layout features contained in an integrated circuit (IC) layout, comprising:

  • generating a plurality of snippet images depicting suspect polygons, each of the snippet images depicting at least a portion of a suspect polygon which is different from a portion of the suspect polygon depicted in others of the plurality of snippet images, the suspect polygons being determined based on the diagnosis of a plurality of defective ICs manufactured according to the IC layout; and

    assigning each of the plurality of snippet images to a particular cluster of a plurality of clusters based on similarities between snippet images in each respective cluster.

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