CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS

• US 20120171859A1
• Filed: 03/08/2012
• Published: 07/05/2012
• Est. Priority Date: 11/02/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ponoth, Shom, Horak, David V., Nogami, Takeshi, Yang, Chih-Chao
• Granted Patent: US 8,703,604 B2
• Time in Patent Office: Days
• US Class Current: 438/620
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

Claims

1. A method comprising:

depositing a plurality of dielectric layers on top of a semiconductor structure, said plurality of dielectric layers being separated by at least one etch-stop layer;

creating multiple openings from a top surface of said plurality of dielectric layers down into said plurality of dielectric layers by a non-selective etching process, wherein at least one of said multiple openings has a depth below said etch-step layer; and

continuing etching said multiple openings by a selective etching process until one or more openings of said multiple openings that are above said etch-stop layer reach and expose said etch-stop layer.

2. The method of claim 1, wherein said etch-stop layer is a first etch-stop layer;

said plurality of dielectric layers are further separated by a second etch-stop layer that is separated from and underneath said first etch-stop layer; and

said at least one of said multiple openings is a first opening;

further comprising creating a second opening of said multiple openings that has a depth below said second etch-stop layer.

3. The method of claim 2, wherein continuing said etching of said multiple openings comprises etching said multiple openings by said selective etching process until said first opening of said multiple openings exposes said second etch-stop layer.

4. The method of claim 3, wherein said semiconductor structure is an interconnect structure of a semiconductor device having a conductive stud, and wherein continuing said etching of said multiple openings comprises etching said multiple openings by said selective etching process until said second opening of said multiple openings exposes said conductive stud.

5. The method of claim 4, further comprising filling in said second opening of said multiple openings with a conductive material thereby forming a conductive via, said conductive via being in contact with said conductive stud of said semiconductor device.

6. The method of claim 2, wherein said first opening has a width that is wider than that of said one or more openings of said multiple openings that are above said first etch-stop layer, and said second opening has a width that is wider than that of said first opening.

7. The method of claim 1, wherein said semiconductor structure is an interconnect structure of a semiconductor device having at least one conductive stud, further comprising etching said multiple openings until said at least one of said multiple openings reaches and exposes said conductive stud.

8. The method of claim 7, wherein said conductive stud is covered by a capping layer before said continuing etching, and wherein continuing said etching of said multiple openings comprises etching said capping layer by another etching process to expose said conductive stud.

9. The method of claim 8, further comprising filling in said at least one of said multiple openings with a conductive material thereby forming a conductive via, said conductive via being in contact with said conductive stud of said semiconductor device.

10. The method of claim 1, wherein said at least one of said multiple openings has a width that is wider than that of said one or more openings of said multiple openings that are above said etch-stop layer.

11. The method of claim 1, further comprising continuing etching said multiple openings by said selective etching process until said etch-stop layer is exposed by two or more openings of said multiple openings that are above said etch-stop layer.

12. The method of claim 1, further comprising filling in said one or more openings of said multiple openings with conductive materials to form one or more trenches.

13. The method of claim 1, wherein said non-selective etching process is non-selective to said etch-stop layer, and said selective etching process is selective to said etch-stop layer and does not etch said etch-stop layer.

14. The method of claim 1, wherein said plurality of dielectric layers are made of SiCOH or silicon oxide and said at least one etch-stop layer is made of amorphous carbon, and wherein said non-selective etching process is a reactive-ion-etch process employing gases of CF₄ and O₂, and wherein said selective etching process is a reactive-ion-etch process containing CF₄.

15. The method of claim 1, wherein said non-selective etching process is a reactive-ion-etching process having a positive etching lag, causing patterns of wider width being etched deeper than patterns of narrower width.

16. The method of claim 1, wherein said top of said semiconductor structure is substantially flat and wherein depositing said plurality of dielectric layers comprises making said top surface of said plurality of dielectric layers to be substantially flat.