Cache Result Register for Quick Cache Information Lookup
First Claim
1. A device comprising:
- at least one processor core;
a memory hierarchy coupled to each of the at least one processor core and including a memory and one or more levels of cache, wherein each cache has a cache result register (CRR) which captures cache access information that can be utilized to access a location at which specific information is stored within the cache; and
transaction address processing logic within each cache of the memory hierarchy that responsive to receipt of a transaction address of a dummy transaction while the one or more levels of caches are in debug mode determines whether the transaction address of the dummy transaction hits within the cache;
wherein in response to a hit of the transaction address of the dummy transaction within the cache, the transaction address processing logic automatically updates the CRR of the cache with the cache access information and passes the transaction address down to a next level of the memory hierarchy; and
wherein in response to a miss of the transaction address of the dummy transaction within the cache, the transaction address processing logic passes the transaction address down to a next level of the memory hierarchy.
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Accused Products
Abstract
Each level of cache within a memory hierarchy of a device is configured with a cache results register (CRR). The caches are coupled to a debugger interface via a peripheral bus. The device is placed in debug mode, and a debugger forwards a transaction address (TA) of a dummy transaction to the device. On receipt of the TA, the device processor forwards the TA via the system bus to the memory hierarchy to initiate an address lookup operation within each level of cache. For each cache in which the TA hits, the cache controller (debug) logic updates the cache'"'"'s CRR with Hit, Way, and Index values, identifying the physical storage location within the particular cache at which the corresponding instruction/data is stored. The debugger retrieves information about the hit/miss status, the physical storage location and/or a copy of the data via direct requests over the peripheral bus.
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Citations
20 Claims
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1. A device comprising:
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at least one processor core; a memory hierarchy coupled to each of the at least one processor core and including a memory and one or more levels of cache, wherein each cache has a cache result register (CRR) which captures cache access information that can be utilized to access a location at which specific information is stored within the cache; and transaction address processing logic within each cache of the memory hierarchy that responsive to receipt of a transaction address of a dummy transaction while the one or more levels of caches are in debug mode determines whether the transaction address of the dummy transaction hits within the cache; wherein in response to a hit of the transaction address of the dummy transaction within the cache, the transaction address processing logic automatically updates the CRR of the cache with the cache access information and passes the transaction address down to a next level of the memory hierarchy; and wherein in response to a miss of the transaction address of the dummy transaction within the cache, the transaction address processing logic passes the transaction address down to a next level of the memory hierarchy. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer implemented method for debugging a device using a debugger, the method comprising:
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forwarding to the device, while the device is in the debug mode, a dummy transaction having a transaction address that triggers a cache access operation within each level of cache to determine whether the transaction address hits within a particular cache; wherein the forwarding of the dummy transaction while the device is in debug mode further triggers each cache to update a cache result register (CRR) of the particular cache with cache access information that indicates whether the transaction address hits within the particular cache, and when the transaction address hits within the particular cache, further indicates a way and an index at which the information corresponding to the transaction address is located within the particular cache; in response to completion of the dummy transaction within the device, triggering a debug probe coupled to the device to retrieve hit/miss information from the CRR and updating a memory window of the debugger with a copy of the data returned from the dummy transaction and hit/miss information corresponding to the dummy transaction for each cache within the memory hierarchy, wherein the debug probe of the debugger coupled to a debug interface of the device detects from each CRR of each cache whether the transaction address from the dummy transaction hit within the particular cache; and in response to the transaction address having hit within the particular cache, retrieves a way indicator value and an index value from the CRR and performs an access to a specific physical location within the cache indicated by the way indicator value and the index value at which the information is stored within the particular cache; wherein each CRR is accessible to the debug interface via a peripheral bus connecting the debug interface to the processor core and to each cache. - View Dependent Claims (12, 13, 14)
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15. A method for enabling debugging within a device having a processor core and a memory hierarchy having one or more levels of cache, the method comprising:
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receiving at the processor core a transaction address associated with a dummy read, while the device is in a debug mode, wherein the processor core and each cache of the device are set to operate in the debug mode; in response to receipt of the transaction address, forwarding the transaction address to a first level cache of a memory hierarchy that includes one or more levels of cache and a memory; determining within each level of the one or more levels of cache whether the transaction address hits; and in response to a hit of the transaction address within a cache, updating a cache result register (CRR) of that particular cache with cache access information including a hit/miss indicator value and a way indicator value and an index value corresponding to a physical location within the particular cache at which the information associated with the transaction address is located. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification