COMPUTER MOTHERBOARD AND CPU VOLTAGE REGULATOR POWER SUPPLY LAYOUT METHOD

• US 20120173892A1
• Filed: 03/23/2011
• Published: 07/05/2012
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Hongfujin Precision Electronics (Tianjin) Co. Ltd.
• Original Assignee: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. (Hon Hai Precision Industry Co., Ltd.), Hon Hai Precision Industry Co., Ltd.
• Inventors: TONG, SONG-LIN, SHEN, LING-LING
• Granted Patent: US 8,739,106 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A computer motherboard includes a motherboard substrate defining a CPU loading area and a CPU voltage regulator power supply layout area. The power supply layout area is equally divided into a number of phase regions, and each of the phase regions has a number of spaced circuit layers. The circuit layers in the phase regions are symmetrical about a central axis of the CPU loading area, and a difference between each two simulating impedances between an impedance center of each of the phase regions and a loading center of the CPU loading area is within 1%.

Claims

1. A computer motherboard comprising a motherboard substrate defining a CPU loading area and a CPU voltage regulator power supply layout area, the power supply layout area being equally divided into a plurality of phase regions, and each of the phase regions having a plurality of spaced circuit layers, the circuit layers in the phase regions being symmetrical about a central axis of the CPU loading area, and a difference between each two simulating impedances between an impedance center of each of the phase regions and a loading center of the CPU loading area being within 1%.

2. The computer motherboard of claim 1, wherein the circuit layers comprises at least a signal layer, a ground layer, and a power layer stacked in an order from a surface of the each of the phase regions.

3. The computer motherboard of claim 2, wherein an order of the circuit layers has the signal layer formed at a bottom, the ground layer formed on the signal layer and the power layer formed on the ground layer, and the circuit layers further comprises an additional power layer formed on the power layer in each of the phase regions.

4. The computer motherboard of claim 2, wherein the circuit layers in each of the phase regions have a plurality of vias formed for electrical connection between adjacent circuit layers, and the vias are symmetrical about the central axis of the CPU loading area.

5. The computer motherboard of claim 4, wherein the number of the vias in each of the phase regions is the same.

6. The computer motherboard of claim 4, wherein the number of the vias in the phase regions farer away from the central axis of the CPU loading area is more than that in the phase regions nearer the central axis of the CPU loading area.

7. The computer motherboard of claim 1, wherein the CPU loading area has at least one CPU socket

8. A CPU voltage regulator power supply layout method, the power supply providing poly-phase electrical power, the method comprising:

providing a motherboard substrate, the motherboard substrate defining a CPU loading area and a CPU voltage regulator power supply layout area;

equally dividing the power supply layout area into a plurality of phase regions;

forming a plurality of circuit layers on one of the phase regions, the circuit layers including at least a signal layer, a ground layer, and a power layer stacked in an order from a surface of each of the phase regions;

forming the same circuit layers to the other phase regions, the circuit layers on the phase regions being symmetrical about a central axis of the CPU loading area;

simulating impedances between an impedance center of each of the phase regions and a loading center of the CPU loading area to determine whether a difference between each of the two simulating impedances is within 1%; and

forming an additional power layer in each of the phase regions if the difference between each of the two simulating impedances is beyond 1% until the difference between each of the two simulating impedances is within 1%.

9. The method of claim 8, wherein an order of the circuit layers has the signal layer formed at a bottom, the ground layer formed on the signal layer, and the power layer formed on the ground layer, and the additional layer is formed on the power layer.

10. The method of claim 8, further comprising forming vias in the circuit layers in each of the phase regions for electrical connection between adjacent circuit layers, and the vias being symmetrical about the central axis of the CPU loading area.