MEMORY SYSTEM AND METHOD OF OPERATING THE SAME

• US 20120173920A1
• Filed: 12/30/2011
• Published: 07/05/2012
• Est. Priority Date: 12/30/2010
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: PARK, Seong Hun
• Application Number:
  US13/340,827
• Publication Number:
  US 20120173920A1
• Time in Patent Office: Days
• US Class Current: 714/6.11
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A method of operating a memory system includes classifying numbers of total error bits into a plurality of ranges, assigning a plurality of data to the plurality of ranges, respectively, counting a number of detected error bits for a memory cell block, and storing a selected one of the plurality of data in at least one spare cell when the number of the detected error bits is within one of the ranges that corresponds to the selected data.

Claims

1. A method of operating a memory system, comprising:

classifying numbers of total error bits into a plurality of ranges;

assigning a plurality of data to the plurality of ranges, respectively;

counting a number of detected error bits for a memory cell block; and

storing a selected one of the plurality of data in at least one spare cell when the number of the detected error bits is within one of the ranges that corresponds to the selected data.

2. The method claim 1, wherein in the range of the number of fail bits, a smallest number of error bits is a valid number of fail bits.

3. The method claim 2, wherein the smallest maximum number indicates a maximum number of total error bits for performing an error correction operation.

4. The method claim 1, wherein the counting of the number of detected error bits comprises performing a test program or an erase operation for the memory cell block and subsequently counting the number of detected error bits.

5. The method claim 4, wherein the test program or erase operation is performed using test data.

6. The method claim 2, wherein the memory cell block is classified as a normal block when an error bit is not generated or the number of detected error bits does not exceed the smallest maximum number.

7. The method claim 6, wherein if the number of detected error bits is greater than the smallest maximum number, the number of detected error bits is compared with the next smallest maximum number.

8. The method claim 1, wherein the at least one spare cell is included in memory cells of the memory cell block.

9. A method of operating a memory system, comprising:

setting a first number of error bits and a second number of fail bits;

assigning first data corresponding to a range of a number of fail bits classified into the first number of error bits and the second number of fail bits;

performing a least significant bit (LSB) program operation for a memory cell block;

storing the first data in at least one spare cell after determining whether a total number of detected error bits after performing the LSB program operation exceeds the first maximum number;

performing a most significant bit (MSB) program operation for the memory cell block; and

storing the second data in the at least one spare cell after determining whether the total number of detected error bits after performing the MSB program operation exceeds the second maximum number.

10. The method claim 9, wherein the first maximum number of error bits and the second maximum number of error bits are the same.

11. The method claim 9, wherein the first and second maximum numbers determine whether the memory cell block is a normal block or a bad block.

12. The method claim 11, wherein the first maximum number indicates a maximum number of error bits for performing an error correction operation.

13. The method claim 9, wherein if the number of detected error bits as a result of the LSB program operation does not exceed the first maximum number of error bits, the MSB program operation for the memory cell block is performed.

14. The method claim 9, wherein if an error cell is not generated as a result of the MSB program operation, the memory cell block is classified as a normal block and data regarding the memory cell block is stored in the at least one spare cell.

15. The method claim 9, wherein if the number of detected error bits as a result of the MSB program operation does not exceed the second maximum number of error bits, the memory cell block is classified as a normal block and data regarding the memory cell block is stored in the at least one spare cell.

16. The method claim 9, wherein the at least one spare cell includes a spare cell to selectively store one of the first data and second data based on the determinations as to whether the total number of detected error bits exceed the first or second maximum number, respectively.

17. A memory system, comprising:

a memory cell array configured to comprise a plurality of memory cell blocks;

a controller configured to determine a bad block in response to comparing the counted number of detected error bits to a maximum number of error bits; and

an error determination circuit for counting a number of detected error bits in the memory cell block as a result of the read operation.

18. The method claim 17, wherein the error determination circuit is configured to output a signal indicating the counted number of detected error bits.

19. The method claim 17, wherein the controller is configured to store data indicating a state of the memory cell block in at least one spare cell corresponding to the memory cell block according to a result of the comparison.