MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
First Claim
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1. A method of operating a memory system, comprising:
- classifying numbers of total error bits into a plurality of ranges;
assigning a plurality of data to the plurality of ranges, respectively;
counting a number of detected error bits for a memory cell block; and
storing a selected one of the plurality of data in at least one spare cell when the number of the detected error bits is within one of the ranges that corresponds to the selected data.
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Abstract
A method of operating a memory system includes classifying numbers of total error bits into a plurality of ranges, assigning a plurality of data to the plurality of ranges, respectively, counting a number of detected error bits for a memory cell block, and storing a selected one of the plurality of data in at least one spare cell when the number of the detected error bits is within one of the ranges that corresponds to the selected data.
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Citations
19 Claims
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1. A method of operating a memory system, comprising:
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classifying numbers of total error bits into a plurality of ranges; assigning a plurality of data to the plurality of ranges, respectively; counting a number of detected error bits for a memory cell block; and storing a selected one of the plurality of data in at least one spare cell when the number of the detected error bits is within one of the ranges that corresponds to the selected data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of operating a memory system, comprising:
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setting a first number of error bits and a second number of fail bits; assigning first data corresponding to a range of a number of fail bits classified into the first number of error bits and the second number of fail bits; performing a least significant bit (LSB) program operation for a memory cell block; storing the first data in at least one spare cell after determining whether a total number of detected error bits after performing the LSB program operation exceeds the first maximum number; performing a most significant bit (MSB) program operation for the memory cell block; and storing the second data in the at least one spare cell after determining whether the total number of detected error bits after performing the MSB program operation exceeds the second maximum number. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A memory system, comprising:
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a memory cell array configured to comprise a plurality of memory cell blocks; a controller configured to determine a bad block in response to comparing the counted number of detected error bits to a maximum number of error bits; and an error determination circuit for counting a number of detected error bits in the memory cell block as a result of the read operation. - View Dependent Claims (18, 19)
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Specification