ERROR CORRECTION CODE BLOCK HAVING DUAL-SYNDROME GENERATOR, METHOD THEREOF, AND SYSTEM HAVING SAME

• US 20120173951A1
• Filed: 12/30/2011
• Published: 07/05/2012
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kong, Jae Phil, Ahn, Seok-Won
• Granted Patent: US 9,246,515 B2
• Time in Patent Office: Days
• US Class Current: 714/755
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/1545 Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial
• CPC Class Codes: H03M 13/159 Remainder calculation, e.g. for encoding and syndrome calculation
• CPC Class Codes: H03M 13/6561 Parallelized implementations

Abstract

An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.

Claims

1. An error correction code (ECC) circuit comprising:

a first syndrome generator;

a second syndrome generator; and

a first selector configured to transmit an even numbered codeword among a plurality of code words, which are input continuously, to the first syndrome generator and configured to transmit an odd numbered codeword among the plurality of code words to the second syndrome generator in response to a first selection signal.

2. The ECC circuit of claim 1, further comprising:

a pulse generator configured to generate a plurality of pulses having a cycle in response to a clock signal; and

a counter configured to count the number of the plurality of pulses and configured to generate the first selection signal according to a count result.

3. The ECC circuit of claim 2, wherein the cycle is determined according to the bit number of each of the plurality of code words.

4. The ECC circuit of claim 1, wherein

the first syndrome generator, based on a previous codeword stored in a first register and a current even-numbered codeword, is configured to calculate syndrome values of the current even numbered codeword and output calculated syndrome values to the first register,

the second syndrome generator, based on a previous codeword stored in a second register and a current odd-numbered codeword, is configured to calculate syndrome values of the current odd-numbered codeword and output calculated syndrome values to the second register.

5. The ECC circuit of claim 4, further comprising:

a second selector configured to transmit syndrome values output from one of the first register and the second register to an error locator polynomial generator circuit in response to a second selection signal.

6. The ECC circuit of claim 1, further comprising:

a second selector configured to transmit one of syndrome values of the even numbered codeword generated by the first syndrome generator and syndrome values of the odd numbered codeword generated by the second syndrome generator to an error locator polynomial generator circuit in response to a second selection signal.

7. The ECC circuit of claim 6, further comprising:

a pulse generator configured to generate a plurality of pulses having a cycle determined according to the bit number of each of the plurality of code words in response to a clock signal;

an one-bit counter configured to count the number of the plurality of pulses and generating a third selection signal;

a third selector configured to output the plurality of pulses output from the pulse generator to one of a first output terminal and a second output terminal according to the third selection signal;

a first counter configured to perform up-count in response to the clock signal after being initialized in response to an output signal of the first output terminal and output a first start signal corresponding to a result of comparing a count value with a reference value;

a first state machine configured to output the second selection signal in response to the first start signal;

a second counter configured to perform up-count in response to the clock signal after being initialized in response to an output signal of the second output terminal and output a second start signal corresponding to a result of comparing a count value with the reference value; and

a second state machine configured to output the second selection signal in response to the second start signal.

8. The ECC circuit of claim 6, wherein the first selector is a de-multiplexer and the second selector is a multiplexer.

9. The ECC circuit of claim 6, further comprising:

a pulse generator configured to generate a plurality of pulses having a cycle determined according to the bit number of each of the plurality of code words in response to a clock signal;

a second selector configured to output an even numbered pulse among the plurality of pulses to a first output terminal and output an odd numbered pulse among the plurality of pulses to a second output terminal in response to the first selection signal;

a first counter configured to count the clock signal after being initialized in response to an output signal of the first output terminal and output a first start signal corresponding to a result of comparing a count value with a reference value;

a first state machine configured to output the second selection signal in response to the first start signal;

a second counter configured to count the clock signal after being initialized in response to an output signal of the second output terminal and output a second start signal corresponding to a result of comparing a count value with the reference value; and

a second state machine configured to output the second selection signal in response to the second start signal.

10. A system comprising:

a first-in first-out (FIFO) buffer configured to receive a plurality of code words output successively from a memory;

a data buffer configured to store the plurality of code words output from the FIFO buffer;

an error correction code (ECC) circuit configured to generate syndrome values by using a syndrome generator, which is selected according to an order of the plurality of code words output from the memory among a plurality of syndrome generators, calculate an error locator polynomial from the generated syndrome values, calculate roots of the calculated error locator polynomial, and output a plurality of error locations from the calculated roots;

a correction direct memory access (DMA) configured to correct an error included in a codeword read from the data buffer by codeword and store an error-corrected codeword in the data buffer by using the plurality of error locations; and

a host interface configured to transmit the error-corrected codeword stored in the correction DMA to a host.

11. The system of claim 10, wherein, when the plurality of syndrome generators include a first syndrome generator and a second syndrome generator, the ECC circuit comprises:

a first selector configured to one of transmit an even numbered codeword among the plurality of code words to the first syndrome generator and transmit an odd numbered codeword among the plurality of code words to the second syndrome generator in response to a first selection signal generated according to the order;

a second selector configured to output syndrome values output from one of the first syndrome generator and the second syndrome generator in response to a second selection signal generated according to the order;

an error locator polynomial generator configured to calculate the error locator polynomial from syndrome values output from the second selector; and

an error locator calculator configured to calculate roots of the error locator polynomial and output the plurality of error locations according to a calculation result.

12. The system of claim 11, wherein the ECC circuit further comprises:

a pulse generator configured to generate a plurality of pulses having a cycle determined according to each bit number of the plurality of code words in response to a clock signal; and

a counter configured to count the number of the plurality of pulses and generate the first selection signal according to a count result.

13. The system of claim 11, when the ECC circuit further comprises:

a first register and a second register,

wherein the first syndrome generator, based on a previous codeword stored in the first register and a current even-numbered codeword, is configured to calculate syndrome values of the current even numbered codeword and output calculated syndrome values to the first register,

wherein the second syndrome generator, based on a previous codeword stored in the second register and a current odd-numbered codeword, is configured to calculate syndrome values of the current odd numbered codeword and output calculated syndrome values to the second register,

wherein the second selection circuit is configured to output syndrome values stored in the first register or the second register to the error locator polynomial generator in response to the second selection signal.

14. The system of claim 10, wherein the system is one of a mobile phone, a smart phone, a tablet PC and a memory card.

15. An error correction code (ECC) circuit, comprising:

at least first and second processing paths;

the first processing path configured to generate syndrome values for a first series of codewords output from a memory;

the second processing path configured to generate syndrome values for a second series of codewords output from the memory, the first and second series of codewords including different codewords.

16. The ECC circuit of claim 15, wherein the first series of codewords includes even numbered codewords output from the memory, and the second series of codewords includes odd numbered codewords output from the memory.

17. The ECC circuit of claim 15, further comprising:

a selector configured to selectively direct the codewords output from the memory to one of the first processing path and the second processing path.

18. The ECC circuit of claim 15, wherein

the first processing path includes a first syndrome generator and a first register, the first syndrome generator is configured to generate syndrome values of a current codeword in the first series of codewords based on a previous codeword in the first series of codewords stored in the first register and the current codeword in the first series of codewords;

and

the second processing path includes a second syndrome generator and a second register, the second syndrome generator is configured to generate syndrome values of a current codeword in the second series of codewords based on a previous codeword in the second series of codewords stored in the second register and the current codeword in the second series of codewords.

19. The ECC circuit of claim 18, further comprising:

an error locator polynomial generator configured to generate one of error locator polynomials and error locator polynomial coefficients from output of the first and second processing paths.

20. The ECC circuit of claim 19, further comprising:

a search block configured to generate error locators based on output from the error locator polynomial generator.