Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound

• US 20120175784A1
• Filed: 03/20/2012
• Published: 07/12/2012
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian, Fang, Jianmin, Chen, Kang, Cao, Haijing
• Granted Patent: US 10,192,801 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.

Claims

1. A semiconductor device, comprising:

a substrate;

a plurality of conductive vias formed in the substrate;

a first semiconductor die mounted over the substrate;

an integrated passive device (IPD) structure formed over the substrate and disposed away from the first semiconductor die;

an encapsulant deposited over the first semiconductor die and IPD structure;

a first interconnect structure formed over a surface of the encapsulant opposite the IPD structure;

a plurality of vertical conductive structures formed through the encapsulant between the IPD structure and first interconnect structure; and

a second interconnect structure formed over a surface of the substrate opposite the IPD structure and electrically connected to the conductive vias.

2. The semiconductor device of claim 1, wherein the IPD structure includes a capacitor.

3. The semiconductor device of claim 1, wherein a thickness of the encapsulant over the IPD structure is at least 50 micrometers.

4. The semiconductor device of claim 1, wherein the first interconnect structure includes an inductor.

5. The semiconductor device of claim 1, wherein the first interconnect structure includes a conductive layer operating as a heat sink.

6. The semiconductor device of claim 1, further including:

a second semiconductor die mounted to the first interconnect structure; and

a third semiconductor die mounted to the second interconnect structure.

7. A semiconductor device, comprising:

a substrate having a plurality of conductive vias formed partially through the substrate;

a first semiconductor die mounted over the substrate;

an integrated passive device (IPD) structure formed over the substrate and disposed away from the first semiconductor die;

an encapsulant deposited over the first semiconductor die and IPD structure; and

a first interconnect structure formed over a surface of the encapsulant opposite the IPD structure.

8. The semiconductor device of claim 7, wherein the IPD structure includes a capacitor.

9. The semiconductor device of claim 7, wherein the first interconnect structure includes an inductor.

10. The semiconductor device of claim 7, further including a heat sink formed over the first interconnect structure.

11. The semiconductor device of claim 7, further including a plurality of vertical conductive structures formed through the encapsulant between the IPD structure and first interconnect structure.

12. The semiconductor device of claim 7, further including a second interconnect structure formed over a surface of the substrate opposite the IPD structure and electrically connected to the conductive vias.

13. The semiconductor device of claim 12, further including a second semiconductor die mounted to the second interconnect structure.

14. A semiconductor device, comprising:

a substrate;

a first semiconductor die mounted over the substrate;

an integrated passive device (IPD) structure formed over the substrate and disposed away from the first semiconductor die;

an encapsulant deposited over the first semiconductor die and IPD structure; and

a first interconnect structure formed over a surface of the encapsulant opposite the IPD structure.

15. The semiconductor device of claim 14, further including a plurality of conductive vias formed in the substrate.

16. The semiconductor device of claim 15, further including a second interconnect structure formed over a surface of the substrate opposite the IPD structure and electrically connected to the conductive vias.

17. The semiconductor device of claim 16, further including a second semiconductor die mounted to the first interconnect structure.

18. The semiconductor device of claim 14, wherein the IPD structure includes a capacitor.

19. The semiconductor device of claim 14, wherein the first interconnect structure includes an inductor.

20. The semiconductor device of claim 14, further including a plurality of vertical conductive structures formed through the encapsulant between the IPD structure and first interconnect structure.

21. A semiconductor device, comprising:

a substrate having a plurality of conductive vias formed partially through the substrate;

a first semiconductor die mounted over the substrate;

an integrated passive device (IPD) structure formed over the substrate and disposed away from the first semiconductor die; and

an encapsulant deposited over the first semiconductor die and IPD structure.

22. The semiconductor device of claim 21, further including:

a first interconnect structure formed over a surface of the encapsulant opposite the IPD structure; and

a second interconnect structure formed over a surface of the substrate opposite the IPD structure and electrically connected to the conductive vias.

23. The semiconductor device of claim 22, further including a second semiconductor die mounted to the first interconnect structure.

24. The semiconductor device of claim 21, wherein the IPD structure includes a capacitor.

25. The semiconductor device of claim 21, further including a plurality of vertical conductive structures formed through the encapsulant between the IPD structure and first interconnect structure.