Systems and methods for precise event timing measurements
First Claim
1. A system for event timing measurement, comprising:
- serializer circuitry having a digital signal pattern as an input and having a bit stream as an output, the digital signal pattern being multi-bit parallel data and the bit stream being single-bit serial data;
logic circuitry having the bit stream as an input and having an event occurrence signal as an input, the logic circuitry being configured to modify the bit stream based upon the event occurrence signal to produce a modified bit stream, the modified bit stream being single-bit serial data;
deserializer circuitry having the modified bit stream as an input and having a modified digital signal pattern as an output, the modified digital signal pattern being multi-bit parallel data; and
event timing detector circuitry configured to compare a predicted digital signal pattern to the modified digital signal pattern to determine when an event occurred within the modified digital signal pattern and to output event timing data representative of when the event occurred within the modified digital signal pattern, the event timing data having a resolution related to a bit period for the modified bit stream.
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Abstract
Systems and methods are disclosed for precise event time measurement. High speed serializer and deserializer circuitry are combined with high speed logic elements, such as exclusive-OR (XOR) or exclusive-not-OR (XNOR) logic circuitry, to achieve a measurement precision based upon a bit period associated with the high speed circuitry rather than upon slower reference clock signals. In certain embodiments, the disclosed systems and methods generate digital signal patterns, serialize them, transmit them as a high speed bit stream, utilize an event occurrence signal and logic circuitry to produce a modified bit stream, deserialize the modified bit stream to produce a modified digital signal pattern, compare the modified signal pattern with a predicted signal pattern, and determine bit positions or bit periods at which events occur based upon this comparison. These bit positions can then be used to generate precise timestamps and related time information for detected events.
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Citations
59 Claims
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1. A system for event timing measurement, comprising:
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serializer circuitry having a digital signal pattern as an input and having a bit stream as an output, the digital signal pattern being multi-bit parallel data and the bit stream being single-bit serial data; logic circuitry having the bit stream as an input and having an event occurrence signal as an input, the logic circuitry being configured to modify the bit stream based upon the event occurrence signal to produce a modified bit stream, the modified bit stream being single-bit serial data; deserializer circuitry having the modified bit stream as an input and having a modified digital signal pattern as an output, the modified digital signal pattern being multi-bit parallel data; and event timing detector circuitry configured to compare a predicted digital signal pattern to the modified digital signal pattern to determine when an event occurred within the modified digital signal pattern and to output event timing data representative of when the event occurred within the modified digital signal pattern, the event timing data having a resolution related to a bit period for the modified bit stream. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A system for signal event timing measurement, comprising:
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a modified signal pattern input, the modified signal pattern input being a modified version of a signal pattern with one or more modifications representing an occurrence of one or more events; deserializer circuitry configured to receive the modified signal pattern input and to have a modified digital signal pattern as an output, the modified digital signal pattern being multi-bit parallel data, and the deserializer circuitry being configured to determine logic levels associated with the modified signal pattern at a first rate and to output the multi-bit parallel data at a second rate wherein the first rate is at least two times faster than the second rate; and event timing detector circuitry configured to compare a predicted signal pattern to the modified digital signal pattern to determine when a modification occurred within the modified digital signal pattern and to output event timing data representative of when the event occurred within the modified digital signal pattern, the event timing data having a resolution related to the first rate. - View Dependent Claims (37, 38, 39, 40, 41)
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42. A method for event timing measurement, comprising:
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outputting a digital signal pattern as multi-bit parallel data; serializing the multi-bit parallel data to generate a bit stream of single-bit serial data; modifying the bit stream using logic circuitry having the bit stream and an event occurrence signal as inputs to generate a modified bit stream of single-bit serial data; deserializing the modified bit stream to generate a modified digital signal pattern as multi-bit parallel data; comparing a predicted digital signal pattern to the modified digital signal pattern to determine when an event occurred within the modified digital signal pattern; and generating event timing data representative of when the event occurred within the modified digital signal pattern, the event timing data having a resolution related to a bit period for the modified bit stream. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59)
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Specification