Asymmetric Multilevel Outphasing Architecture For RF Amplifiers

• US 20120176195A1
• Filed: 03/19/2012
• Published: 07/12/2012
• Est. Priority Date: 11/11/2008
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Dawson, Joel L., Perreault, David J., Chung, SungWon, Godoy, Philip, Huang, Everest
• Granted Patent: US 8,659,353 B2
• Time in Patent Office: Days
• US Class Current: 330/124.R
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/0294 using vector summing of two or more constant amplitude phase-modulated signals
• CPC Class Codes: H03F 2200/516 Some amplifier stages of an amplifier use supply voltages of different value
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/2176 Class E amplifiers
• CPC Class Codes: H03F 3/602 Combinations of several amplifiers

Abstract

A radio frequency (RF) circuit includes a power supply configured to generate a plurality of voltages, a plurality of power amplifiers, each having an RF output port and a power supply input port, a switch network having a plurality of input ports coupled to the power supply and a plurality of switch network output ports coupled to the power supply input ports of the plurality of power amplifiers, wherein the switch network is configured to output selected ones of the plurality of voltages from the plurality of switch network output ports, at least two of the switch network output port voltages capable of being different ones of the plurality of voltages, and an RF power combiner circuit having a plurality of input ports coupled to RF output ports of the plurality of power amplifiers and an output port at which is provided an output signal of the RF circuit.

Claims

1. A radio frequency circuit comprising:

a plurality of power amplifiers, each having at least one input port and an RF output port, wherein each power amplifier is configured to selectively provide an output signal having one of a plurality of discrete output amplitudes and an adjustable phase at its output port, at least two of the output signal amplitudes from different power amplifiers capable of being different ones of the plurality of discrete output amplitudes;

an RF power combiner circuit having a plurality of input ports coupled to RF output ports of the plurality of power amplifiers and an output port at which is provided an output signal of the RF circuit; and

a control system coupled to the at least one input port of each power amplifier and configured to control the output signal of the RF circuit by adjusting the phase and selecting the amplitudes of the output signals of said power amplifiers.

2. The RF circuit of claim 1, wherein each of the power amplifiers has a power supply input port configured to receive a power supply input voltage, and comprising:

a power supply circuit having a set of output ports coupled to the power supply input ports of the power amplifiers, and configured to selectively provide one of a plurality of supply voltages to each of the power supply input ports of the power amplifiers,

wherein the discrete output amplitude provided by each power amplifier is controlled by selecting a particular power supply input voltage provided at the power supply input port of each power amplifier.

3. The RF circuit of claim 2 wherein said power supply circuit further comprises a switched-capacitor power supply that synthesizes the plurality of supply voltages selectively provided at the power supply input ports of the power amplifiers.

4. The RF circuit of claim 1 wherein the power combiner further includes an energy recovery network comprising at least one rectifier.

5. The RF circuit of claim 4 wherein the energy recovery network comprises a resistance-compressed rectifier.

6. The RF circuit of claim 5, wherein the resistance-compressed rectifier further includes at least two levels of resistance compression.

7. The RF circuit of claim 5 wherein the resistance compressed rectifier comprises:

a plurality of rectifiers; and

a resistance compression network.

8. The RF circuit of claim 5 wherein the energy recovery network further includes a tuned network that suppresses the harmonic content produced by rectifier operation.

9. The RF circuit of claim 5 wherein the energy recovery network further comprises an isolator.

10. The RF circuit of claim 9 wherein said isolator is disposed in front of a resistance compressed rectifier.

11. The RF circuit of claim 4 wherein the energy recovery network comprises:

a plurality of rectifiers; and

a lossless circuit coupling the [energy recovery input] to the plurality of rectifiers, wherein the input resistance of the energy recovery input varies over a first ratio as the input resistances of the plurality of rectifiers vary over a second ratio that is larger than the first ratio.