REDUCING RECURRENT COMPUTATION COST IN A DATA PROCESSING PIPELINE

• US 20120176386A1
• Filed: 01/09/2012
• Published: 07/12/2012
• Est. Priority Date: 01/10/2011
• Status: Abandoned Application

• Current Assignee: Edward A. Hutchins
• Original Assignee: Edward A. Hutchins
• Inventors: Hutchins, Edward A.
• Application Number:
  US13/346,364
• Publication Number:
  US 20120176386A1
• Time in Patent Office: Days
• US Class Current: 345/522
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

Briefly, in accordance with one or more embodiments of graphics processing, a current data signature is generated based at least in part on current input data, and the current data signature is compared with a prior cycle data signature. If the current data signature at least partially matches the prior cycle data signature, a prior cycle result may be fetched and processing of at least part of the current input data may be skipped.

Claims

1. An article of manufacture comprising a storage medium having instructions stored thereon that, if executed, result in:

generating a current data signature based at least in part on current input data;

comparing the current data signature to a prior cycle data signature; and

if the current data signature at least partially matches the prior cycle data signature, fetching a prior cycle result and foregoing processing of at least part of the current input data.

2. An article of manufacture as claimed in claim 1, wherein data is divided into N blocks, said generating comprising generating a current data signature for block N, and said comparing comprising comparing the current data signature for block N to a prior data signature for block N.

3. An article of manufacture as claimed in claim 2, said fetching comprising fetching a prior cycle result, and said foregoing processing comprising foregoing processing of at least part of the current input data if the current data signature for block N at least partially matches the prior cycle data signature for block N.

4. An article of manufacture as claimed in claim 1, wherein data is divided into N blocks, and the N blocks are divided into K processing steps, said generating comprising generating a current data signature for block N and processing step K, and said comparing comprising comparing the current data signature for block N and processing step K to a prior data signature for block N and processing step K.

5. An article of manufacture as claimed in claim 4, said fetching comprising fetching a prior cycle result, and said foregoing processing comprising foregoing processing of at least part of the current input data if the current data signature for block N and processing step K at least partially matches the prior cycle data signature for block N and processing step K.

6. A method as claimed in claim 1, wherein the current data signature or the prior cycle data signature comprises a dynamic signature portion based at least in part on dynamic input data, or a static signature portion based at least in part on static input data, or combinations thereof.

7. An article of manufacture as claimed in claim 6, wherein the static signature portion is pre-calculated without requiring said generating for a given processing cycle.

8. An article of manufacture as claimed in claim 1, wherein the instructions, if executed, further result in:

dividing the current input data into two or more tiles;

said generating comprising generating a command signature for the two or more tiles and storing the command signatures in a respective tile command buffer; and

said comparing comprising comparing a command signature of a current input data tile command buffer with a command signature of a prior cycle tile command buffer.

9. An article of manufacture as claimed in claim 1, wherein the instructions, if executed, further result in:

processing pixel transactions for one or more pixels of the current input data;

said generating comprising generating a pixel signature for the one or more pixels and storing the pixel signatures in a pixel signature buffer; and

said comparing comprising comparing a pixel signature of a current data pixel signature buffer with a pixel signature of a prior cycle pixel signature buffer.

10. A graphics processor, comprising:

a data signature generator circuit to generate a current data signature based at least in part on current input data;

a compare circuit to compare the current data signature to a prior cycle data signature; and

a computation circuit to fetch a prior cycle result and forego processing of at least part of the current input data if the current data signature at least partially matches the prior cycle data signature.

11. A graphics processor as claimed in claim 10, further comprising:

a divider circuit to divide data into N blocks;

said data signature generator circuit being configured to generate a current data signature for block N; and

said compare circuit being configured to compare the current data signature for block N to a prior data signature for block N.

12. A graphics processor as claimed in claim 11, further comprising:

said computation circuit being configured to fetch a prior cycle result and forego processing of at least part of the current input data if the current data signature for block N at least partially matches the prior cycle data signature for block N.

13. A graphics processor as claimed in claim 10, further comprising:

a divider circuit to divide data into N blocks, and to divide the N blocks into K processing steps;

said data signature generator being configured to generate a current data signature for block N and processing step K; and

said compare circuit being configured to compare the current data signature for block N and processing step K to a prior data signature for block N and processing step K.

14. A graphics processor as claimed in claim 13, wherein the computation circuit is configured to fetch a prior cycle result and forego processing of at least part of the current input data if the current data signature for block N and processing step K at least partially matches the prior cycle data signature for block N and processing step K.

15. A graphics processor as claimed in claim 10, wherein the current data signature or the prior cycle data signature comprises a dynamic signature portion based at least in part on dynamic input data, and a static signature portion based at least in part on static input data.

16. A graphics processor as claimed in claim 15, wherein the computation circuit is configured to pre-calculate the static signature portion without requiring generation of the static signature portion for a given processing cycle.

17. A graphics processor as claimed in claim 10, further comprising:

a tile processor circuit to divide the current input data into two or more tiles;

a command signature generator circuit to generate a command signature for the two or more tiles and store the command signatures in a respective tile command buffer; and

a command signature checker circuit to compare a command signature of a current input data tile command buffer with a command signature of a prior cycle tile command buffer.

18. A graphics processor as claimed in claim 10, further comprising:

a pixel rasterizer to process pixel transactions for one or more pixels of the current input data;

a pixel signature generator circuit to generate a pixel signature for the one or more pixels and store the pixel signatures in a pixel signature buffer; and

a pixel signature checker circuit to compare a pixel signature of a current data pixel signature buffer with a pixel signature of a prior cycle pixel signature buffer.

19. An information handling system, comprising:

a baseband processor coupled to one or more wireless transceivers; and

an applications processor coupled to the baseband processor, wherein the applications processor is configured to;

generate a current data signature based at least in part on current input data;

compare the current data signature to a prior cycle data signature; and

if the current data signature at least partially matches the prior cycle data signature, fetch a prior cycle result and forego processing of at least part of the current input data.

20. An information handling system as claimed in claim 19, further comprising:

a tile processor circuit to divide the current input data into two or more tiles;

a command signature generator circuit to generate a command signature for the two or more tiles and store the command signatures in a respective tile command buffer;

a command signature checker circuit to compare a command signature of a current input data tile command buffer with a command signature of a prior cycle tile command buffer;

a pixel rasterizer to process pixel transactions for one or more pixels of the current input data;

a pixel signature generator circuit to generate a pixel signature for the one or more pixels and store the pixel signatures in a pixel signature buffer; and

a pixel signature checker circuit to compare a pixel signature of a current data pixel signature buffer with a pixel signature of a prior cycle pixel signature buffer.