COMMUNICATION CIRCUIT AND METHOD OF ADJUSTING SAMPLING CLOCK SIGNAL
First Claim
1. A communication circuit that receives communication data in asynchronous serial communications, the communication circuit comprising:
- a sampling clock generating circuit configured to generate a sampling clock signal having a frequency that is “
m”
times greater than a it rate of the communication data and containing “
n”
pulses in each bit period of the communication data, “
m”
being an integer greater than or equal to 4, “
n”
being an odd number less than “
m”
;
a sampling circuit configured to sample the communication data based on the sampling clock signal to obtain “
n”
sets of received data in each bit period of the communication data; and
a majority circuit configured to perform a majority operation on values of the “
n”
sets of received data to determine a majority value and to output the majority value as received data of the corresponding bit period,wherein the sampling clock generating circuit is configuredto delay the sampling clock signal by a predetermined amount when a value of a first one or more of the “
n”
sets of received data is different from a value of a rest of the “
n”
sets of received data, andto advance the sampling clock signal by the predetermined amount when a value of a last one or more of the “
n”
sets of received data is different from a value of a rest of the “
n”
sets of received data.
1 Assignment
0 Petitions
Accused Products
Abstract
A communication circuit includes a sampling clock generating circuit generating a sampling clock signal having a frequency that is “m” times greater than a bit rate of the communication data and containing “n” pulses in each bit period of the communication data; and a sampling circuit sampling the communication data based on the sampling clock signal to obtain “n” sets of received data in each bit period of the communication data. The sampling clock generating circuit delays the sampling clock signal when a first one or more of the “n” sets of received data are different from a value of the rest of the “n” sets of received data, and advances the sampling clock signal when a value of a last one or more of the “n” sets of received data is different from a value of the rest of the “n” sets of received data.
-
Citations
9 Claims
-
1. A communication circuit that receives communication data in asynchronous serial communications, the communication circuit comprising:
-
a sampling clock generating circuit configured to generate a sampling clock signal having a frequency that is “
m”
times greater than a it rate of the communication data and containing “
n”
pulses in each bit period of the communication data, “
m”
being an integer greater than or equal to 4, “
n”
being an odd number less than “
m”
;a sampling circuit configured to sample the communication data based on the sampling clock signal to obtain “
n”
sets of received data in each bit period of the communication data; anda majority circuit configured to perform a majority operation on values of the “
n”
sets of received data to determine a majority value and to output the majority value as received data of the corresponding bit period,wherein the sampling clock generating circuit is configured to delay the sampling clock signal by a predetermined amount when a value of a first one or more of the “
n”
sets of received data is different from a value of a rest of the “
n”
sets of received data, andto advance the sampling clock signal by the predetermined amount when a value of a last one or more of the “
n”
sets of received data is different from a value of a rest of the “
n”
sets of received data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A method performed by a communication circuit that receives communication data in asynchronous serial communications, the method comprising:
-
generating a sampling clock signal having a frequency that is “
m”
times greater than a bit rate of the communication data and containing “
n”
pulses in each bit period of the communication data, “
m”
being an integer greater than or equal to 4, “
n”
being an odd number less than “
m”
;sampling the communication data based on the sampling clock signal to obtain “
n”
sets of received data in each bit period of the communication data;performing a majority operation on values of the “
n”
sets of received data to determine a majority value and outputting the majority value as received data of the corresponding bit period;delaying the sampling clock signal by a predetermined amount when a value of a first one or more of the “
n”
sets of received data is different from a value of a rest of the “
n”
sets of received data; andadvancing the sampling clock signal by the predetermined amount when a value of a last one or more of the “
n”
sets of received data is different from a value of a rest of the “
n”
sets of received data.
-
Specification