CO-PACKAGING APPROACH FOR POWER CONVERTERS BASED ON PLANAR DEVICES, STRUCTURE AND METHOD

• US 20120178211A1
• Filed: 03/20/2012
• Published: 07/12/2012
• Est. Priority Date: 12/23/2008
• Status: Abandoned Application

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Hebert, Francois
• Application Number:
  US13/424,421
• Publication Number:
  US 20120178211A1
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66696 : with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a planar vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the power die.

Claims

1. A method of forming a semiconductor circuit, comprising:

forming a high-side transistor comprising a lateral diffusion metal oxide semiconductor (LDMOS) device on a substrate of a semiconductor die;

forming a low-side transistor comprising a vertical diffusion metal oxide semiconductor (VDMOS) device on the substrate of the semiconductor die; and

forming a single conductive structure which forms;

a gate shield which is interposed between at least one conductive gate portion of the LDMOS device and a conductive structure which overlies the gate shield; and

a trench conductor electrically coupled to the substrate of the semiconductor die and to a source region of the LDMOS device.

2. The method of claim 1 wherein the semiconductor die is a first semiconductor die, and the method further comprises:

forming a voltage converter controller circuit on a second semiconductor die different from the first semiconductor die; and

electrically coupling an output circuit on the first semiconductor die comprising the LDMOS device and the VDMOS device to the controller circuit on the second semiconductor die.

3. The method of claim 2, further comprising co-packaging the first semiconductor die and the second semiconductor die into a single semiconductor device.

4. The method of claim 1 further comprising forming a second single conductive structure which forms:

a drain interconnect which electrically couples a drain of the LDMOS device to voltage in (V_IN); and

a source interconnect which electrically couples a source of the VDMOS device to ground.

5. The method of claim 1, wherein forming the high-side transistor and forming the low-side transistor further comprises forming the high-side transistor and forming the low-side transistor such that the LDMOS device and the VDMOS device are electrically coupled to one another via the substrate

6. The method of claim 5, wherein forming the high-side transistor and forming the low-side transistor further comprises forming the high-side transistor and forming the low-side transistor such that a source of the LDMOS is electrically coupled to a drain of the VDMOS via the substrate.

7. The method of claim 1, wherein the substrate of the semiconductor die has a back side and the formation of the high-side transistor and the low-side transistor forms an output stage of the semiconductor circuit;

the method further comprising;

doping the substrate to a dopant concentration of about 1E18 to 1E20 atoms/cm³ such that, during operation of the semiconductor circuit, the back side of the substrate is adapted to function as a switched node of the output stage.

8. The method of claim 1, wherein forming the high-side transistor includes patterning a gate conductor layer to form a gate of the LDMOS device;

and

wherein forming the low-side transistor includes patterning said gate conductor layer to form a gate of the VDMOS device such that the gate of the LDMOS device and the gate of the VDMOS device are coplanar.

9. A method of forming a semiconductor circuit having a high-side lateral diffusion metal oxide semiconductor (LDMOS) device and a low-side vertical diffusion metal oxide semiconductor (VDMOS) device on a shared substrate of a semiconductor die, the method comprising:

patterning a blanket gate conductor layer to form at least one gate of the LDMOS device and at least one gate of the VDMOS device; and

forming a gate shield and a trench conductor from a shared conductive structure;

wherein the gate shield overlies the at least one gate of the LDMOS device; and

wherein the trench conductor is electrically coupled to the substrate and to a source region of the LDMOS device.

10. The method of claim 9, wherein patterning the gate conductor layer comprises patterning the gate conductor layer such that the at least one gate of the LDMOS device and the at least one gate of the VDMOS device are coplanar.

11. The method of claim 9, further comprising:

simultaneously forming a body diffusion region of the LDMOS device and a body region of the VDMOS device from a shared body implant.

12. The method of claim 9, further comprising:

simultaneously forming a source region of the LDMOS device and a source region of the VDMOS device from a shared source implant.

13. The method of claim 9, further comprising:

forming a drain interconnect and a source interconnect from a single conductive structure, the drain interconnect electrically coupling a drain of the LDMOS device to an input voltage and the source interconnect electrically coupling a source of the VDMOS device to ground.

14. The method of claim 9 wherein the semiconductor die is a first semiconductor die and the method further comprises:

forming a voltage converter controller circuit on a second semiconductor die different from the first semiconductor die; and

electrically coupling an output circuit on the first semiconductor die comprising the LDMOS device and the VDMOS device to the controller circuit on the second semiconductor die.

15. The method of claim 14, further comprising co-packaging the first semiconductor die and the second semiconductor die into a single semiconductor device.

16. The method of claim 9, wherein forming a gate shield and a trench conductor from a shared conductive structure comprises:

forming a blanket dielectric layer;

forming a first patterned mask over the blanket dielectric layer that leaves uncovered portions of the dielectric layer that overlie high-side source regions and a high-side body contact region;

etching the uncovered portions of the dielectric layer;

forming a second patterned mask which defines a trench opening for the trench conductor;

etching through portions of the body contact region and the high-side source regions that are within the opening defined by the second patterned mask to expose a portion of the shared substrate; and

forming one or more conductive layers within the trench opening and over the dielectric layer.

17. The method of claim 9, wherein forming a gate shield and a trench conductor from a shared conductive structure comprises:

forming a blanket dielectric layer;

forming a patterned substrate contact mask which exposes a portion of the blanket dielectric layer to define a trench opening for the trench conductor;

etching through portions of the of a high-side body contact region and high-side source regions that are within the opening defined by the patterned substrate contact mask to expose a portion of the shared substrate; and

forming one or more conductive layers within the trench opening and over the dielectric layer.

18. The method of claim 9, further comprising using a buried layer to form a deep body region of the high-side LDMOS device.

19. The method of claim 9, wherein forming the gate shield and the trench conductor from the shared conductive structure comprises:

forming a first gate shield and a first trench conductor from the shared conductive structure on a first side of the LDMOS device, the first gate shield overlying a first gate of the LDMOS device; and

forming a second gate shield and a second trench conductor from the shared conductive structure on a second side of the LDMOS device, the second gate shield overlying a second gate of the LDMOS device.

20. The method of claim 9, further comprising:

using a patterned buried layer to control up-diffusion of an implant into an drift region of the high-side LDMOS device, the patterned buried layer having a first conductivity type and the drift region having a second conductivity type.