CO-PACKAGING APPROACH FOR POWER CONVERTERS BASED ON PLANAR DEVICES, STRUCTURE AND METHOD
First Claim
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1. A method of forming a semiconductor circuit, comprising:
- forming a high-side transistor comprising a lateral diffusion metal oxide semiconductor (LDMOS) device on a substrate of a semiconductor die;
forming a low-side transistor comprising a vertical diffusion metal oxide semiconductor (VDMOS) device on the substrate of the semiconductor die; and
forming a single conductive structure which forms;
a gate shield which is interposed between at least one conductive gate portion of the LDMOS device and a conductive structure which overlies the gate shield; and
a trench conductor electrically coupled to the substrate of the semiconductor die and to a source region of the LDMOS device.
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Abstract
A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a planar vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the power die.
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Citations
20 Claims
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1. A method of forming a semiconductor circuit, comprising:
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forming a high-side transistor comprising a lateral diffusion metal oxide semiconductor (LDMOS) device on a substrate of a semiconductor die; forming a low-side transistor comprising a vertical diffusion metal oxide semiconductor (VDMOS) device on the substrate of the semiconductor die; and forming a single conductive structure which forms; a gate shield which is interposed between at least one conductive gate portion of the LDMOS device and a conductive structure which overlies the gate shield; and a trench conductor electrically coupled to the substrate of the semiconductor die and to a source region of the LDMOS device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a semiconductor circuit having a high-side lateral diffusion metal oxide semiconductor (LDMOS) device and a low-side vertical diffusion metal oxide semiconductor (VDMOS) device on a shared substrate of a semiconductor die, the method comprising:
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patterning a blanket gate conductor layer to form at least one gate of the LDMOS device and at least one gate of the VDMOS device; and forming a gate shield and a trench conductor from a shared conductive structure; wherein the gate shield overlies the at least one gate of the LDMOS device; and wherein the trench conductor is electrically coupled to the substrate and to a source region of the LDMOS device. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification