Method for Forming Accumulation-mode Field Effect Transistor with Improved Current Capability

• US 20120178228A1
• Filed: 04/08/2011
• Published: 07/12/2012
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Shenoy, Praveen Muraleedharan, Koon, Christopher Boguslaw
• Granted Patent: US 8,518,777 B2
• Time in Patent Office: Days
• US Class Current: 438/238
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 : Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7838 : without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A method of forming an accumulation-mode field effect transistor includes forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type. The channel region may extend from a top surface of the semiconductor region to a first depth within the semiconductor region. The method also includes forming gate trenches in the semiconductor region. The gate trenches may extend from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth. The method also includes forming a first plurality of silicon regions of a second conductivity type in the semiconductor region such that the first plurality of silicon regions form P-N junctions with the channel region along vertical walls of the first plurality of silicon regions.

Claims

1-102. -102. (canceled)

103. A method of forming an accumulation-mode field effect transistor, the method comprising:

forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type, the channel region extending from a top surface of the semiconductor region to a first depth within the semiconductor region;

forming gate trenches in the semiconductor region, the gate trenches extending from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth; and

forming a first plurality of silicon regions of a second conductivity type in the semiconductor region such that the first plurality of silicon regions form P-N junctions with the channel region along vertical walls of the first plurality of silicon regions.

104. The method of claim 103 wherein the first plurality of silicon regions and the gate trenches are alternately arranged so that each of the first plurality of silicon regions is between but laterally spaced from two adjacent gate trenches.

105. The method of claim 103 wherein conduction channels are formed in the channel region along the sidewalls of the gate trenches when the accumulation-mode field effect transistor is in the on state.

106. The method of claim 103 wherein the step of forming a first plurality of silicon regions comprises:

forming body trenches in the semiconductor region, the body trenches extending from the top surface of the semiconductor region to a depth within the semiconductor region below the first depth; and

substantially filling the body trenches with silicon material of the second conductivity type, wherein the body trenches and the gate trenches are alternately arranged so that each body trench is between but laterally spaced from two adjacent gate trenches.

107. The method of claim 103 wherein the first plurality of silicon regions are formed by implanting dopants of the second conductivity type into the semiconductor region.

108. The method of claim 103 further comprising:

forming a gate electrode in each gate trench, the gate electrode being adjacent to but insulated from the channel region.

109. The method of claim 103 wherein the semiconductor region includes an epitaxial layer extending over and in contact with a substrate, the substrate and the epitaxial layer being the first conductivity type, the epitaxial layer having a lower doping concentration than the substrate, and wherein the channel region, the trenches and the first plurality of silicon regions extend into the epitaxial layer.

110. The method of claim 103 further comprising:

forming a second plurality of silicon regions of the first conductivity type in the channel region such that each pair of the second plurality of silicon regions flanks sides of a corresponding one of the gate trenches, wherein the second plurality of silicon regions have a higher doping concentration than that of the channel region.

111. The method of claim 110 further comprising:

forming a resistor coupled between the first plurality of silicon regions and the second plurality of silicon regions.

112. The method of claim 103 wherein the gate trenches and the first plurality of silicon regions are parallel-extending continuous stripes.

113. The method of claim 103 wherein the first plurality of silicon regions are formed in the semiconductor region such that an upper-most surface of each of the first plurality of silicon regions is below the top surface of the semiconductor region.

114. The method of claim 103 further comprising:

forming columns of silicon of the second conductivity type in the semiconductor region so that the columns of silicon of the second conductivity type and the semiconductor region together form alternating columns of first and second conductivity type silicon, wherein no current flows through the columns of silicon of the second conductivity type when the accumulation-mode field effect transistor is in the on state.

115. The method of claim 114 wherein each of the columns of silicon of the second conductivity type extend directly below a corresponding one of the plurality of first silicon regions.