METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE
First Claim
1. A method of manufacturing an integrated circuit device, comprising:
- preparing a substrate having an active region defined by a device isolation layer;
forming a resistor pattern on the device isolation layer, the resistor pattern including a resistor body positioned in a recess portion of the device isolation layer and at least a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion, the connector having a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion thereof;
forming a gate pattern on the active region of the substrate, the gate pattern including the metal silicide pattern at an upper portion thereof; and
forming a resistor interconnection making contact with the connector of the resistor pattern.
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Accused Products
Abstract
In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.
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Citations
25 Claims
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1. A method of manufacturing an integrated circuit device, comprising:
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preparing a substrate having an active region defined by a device isolation layer; forming a resistor pattern on the device isolation layer, the resistor pattern including a resistor body positioned in a recess portion of the device isolation layer and at least a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion, the connector having a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion thereof; forming a gate pattern on the active region of the substrate, the gate pattern including the metal silicide pattern at an upper portion thereof; and forming a resistor interconnection making contact with the connector of the resistor pattern. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16-20. -20. (canceled)
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21. A method of manufacturing an integrated circuit device, comprising:
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forming one or more device isolation layers on a cell area and a peripheral area of a substrate; forming a resistor pattern having a resistor body having a first electric resistance and a connector having a second electric resistance lower than the first electric resistance, on the device isolation layers of a resistor portion of the peripheral area of the substrate; and forming a resistor interconnection to contact the connector of the resistor pattern to reduce a contact resistance therebetween. - View Dependent Claims (22, 23, 24)
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25-28. -28. (canceled)
Specification