VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR

• US 20120179409A1
• Filed: 01/06/2011
• Published: 07/12/2012
• Est. Priority Date: 01/06/2011
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Montrose, Charles J., Wang, Ping-Chuan
• Granted Patent: US 9,043,179 B2
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory

Abstract

A system for testing a plurality of transistors on a wafer having a storage device or personal computer connected via a bus to a plurality of drivers. Each of the voltage drivers having a microcontroller adapted to receive test parameters and provide test data from a plurality of voltage drivers. By utilizing a bus structure, the personal computer can look on one bus for flags indicating test data is available from a driver and receive the data. In addition a bus may be used to provide test parameters to the drivers. In this manner, multiple drivers may be run at the same time incorporating multiple tests. When data is available it is transferred to the personal computer, for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers.

Claims

1. A system comprising:

a storage device for storing data;

a plurality of drivers, the drivers connected to the storage device via a bus, the drivers adapted to be connected to a plurality of devices under test (DUTs);

whereby the drivers are adapted to test the plurality of DUTs in parallel, and provide data from the test to the storage device.

2. The system of claim 1, wherein the storage device further provides test parameters to the drivers.

3. The system of claim 1 wherein the bus is a dual unidirectional 8-bit hand shaked data bus.

4. The system of claim 1, wherein the storage device is a computer.

5. The system of claim 2, wherein the storage device provides test parameters to a driver after the driver provides test data.

6. The system of claim 1, wherein the drivers provide a flag when data is available for the storage device.

7. The system of claim 2, wherein the drivers comprise a first voltage driver having a first input;

a ground;

a microcontroller; and

a buffer, wherein the microcontroller is adapted to receive test parameters from the storage device, set test parameters in the first voltage driver;

the first voltage driver is adapted to provide test data to the buffer.

8. The system of claim 7, wherein the drivers comprise a second voltage driver, the second voltage driver sharing a ground with the first voltage driver.

9. The system of claim 8, wherein the first and second voltage drivers have test outputs and data inputs adapted to be connected to the DUTs via probes.

10. The system of claim 8, wherein the first and second voltage drivers have test outputs and data inputs adapted to be connected to the DUTs via wire bonds.

11. The system of claim 9, wherein the data inputs are set to ground prior to connecting the system to a DUT.

12. The system of claim 9, wherein the data inputs are set to ground prior to connecting the system to a DUT.

13. The system of claim 9, wherein the drivers provide a flag when data is available for the storage device.

14. The system of claim 13, wherein the storage device provides test parameters to a driver after the driver provides test data.

15. A system for testing a plurality of transistors on a wafer comprising:

a personal computer connected via a first bus for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers;

the plurality of drivers being adapted to be connected to a plurality of transistors on a wafer, each of the plurality of drivers comprises a first voltage driver having a first output adapted to be connected to a drain of a transistor, a second voltage driver having a second output adapted to be connected to a gate of the transistor, and a ground having a third output adapted to be connected to the drain of the transistor, a microcontroller for receiving test parameters from the personal computer, transmitting test parameters to the first and second voltage drivers, receiving test results from the first and second voltage driver and providing the test results to the personal computer.

16. The system of claim 15, wherein the first and second outputs can be connected to the ground.

17. The system of claim 16, wherein the first and second outputs are connected to ground prior to connecting the system to a DUT.

18. The system of claim 17, wherein the first, second and third outputs are probes.

19. The system of claim 17, wherein the first, second and third outputs are wire bonds.

20. The system of claim 19, wherein the first, second and third outputs are optically isolated from the microcontroller.