MECHANISM TO SUPPORT FLEXIBLE DECOUPLED TRANSACTIONAL MEMORY

• US 20120179877A1
• Filed: 03/16/2012
• Published: 07/12/2012
• Est. Priority Date: 08/15/2007
• Status: Active Grant

• Current Assignee: University Of Rochester, Office Of Technology Transfer
• Original Assignee: University Of Rochester, Office Of Technology Transfer
• Inventors: SHRIRAMAN, Arrvindh, DWARKADAS, Sandhya, SCOTT, Michael
• Granted Patent: US 8,661,204 B2
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 9/524 Deadlock detection or avoidance
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

The present invention employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables, which identify the threads with which conflicts have occurred; and a lazy versioning mechanism, which maintains the speculative updates in the local cache and employs a thread-private buffer (in virtual memory) only in the rare event of an overflow. The conflict summary tables allow lazy conflict management to occur locally, with no global arbitration (they also support eager management). All three mechanisms are kept software-accessible, to enable virtualization and to support transactions of arbitrary length.

Claims

1. A method of decoupling the detection of conflicting concurrent accesses to memory from the action taken in response to the detected conflicts, in a shared-memory multiprocessor, the method comprising:

providing a plurality of processor cores that indicate when certain reads and writes are speculative, wherein reads and writes of each processor core in the plurality of processors cores are monitored for conflicts with the reads and writes of other processor cores in the plurality of processor cores and can be rolled back;

permitting the local caches of the plurality of processor cores to retain copies of speculatively read or written lines despite conflicting reads or writes to those lines by the other process cores in the plurality of processor cores;

and

maintaining for each processor core in the plurality of processor cores a concise, software-visible indication of the other processor cores in plurality whose speculative reads or writes conflict with the speculative reads or writes of a processor core for which the indication is being maintained.

2. The method of claim 1, further comprising maintaining the indication of conflicts for each processor core in the plurality of processor cores as a vector with an entry for each other processor core in the plurality of processor cores.

3. The method of claim 1, further comprising:

virtualizing conflict information across context switches on a per-thread basis.

4. The method of claim 1, further comprising:

arbitrating conflicts and committing transactions without broadcast or centralized control using a transactional memory in which the plurality of processor cores use their record of conflicting computations.

5. The method of claim 4, wherein, at a time prior to committing a transaction, performing by a core processor in the plurality of core processors an operation to abort speculation in each remote computation with which it conflicts.

6. The method of claim 1, further comprising:

providing a concise record of certain cache lines recently read from and written to, wherein this record is used, on each cache coherence protocol interaction, to update per-core vectors, visible to software, that indicate conflicts with computations on other cores.

7. A system for decoupling the detection of conflicting concurrent accesses to memory from the action taken in response to the detected conflicts, in a shared-memory multiprocessor, the system comprising:

a plurality of processor cores that indicate when certain reads and writes are speculative, wherein reads and writes of each processor core in the plurality of processors cores are monitored for conflicts with the reads and writes of other processor cores in the plurality of processor cores and can be rolled back; and

local caches of the plurality of processor cores retaining copies of speculatively read or written lines despite conflicting reads or writes to those lines by the other process cores in the plurality of processor cores;

wherein for each processor core in the plurality of processor cores there is maintained a concise, software-visible indication of the other processor cores in plurality whose speculative reads or writes conflict with the speculative reads or writes of a processor core for which the indication is being maintained.

8. The system of claim 7, wherein maintaining the indication of conflicts for each processor core in the plurality of processor cores is implemented as a vector with an entry for each other processor core in the plurality of processor cores.

9. The system of claim 7, wherein conflict information is virtualized across context switches on a per-thread basis.

10. The system of claim 7, further comprising a transactional memory in which the plurality of processor cores use their record of conflicting computations, wherein conflicts are arbitrated and transactions committed without broadcast or centralized control.

11. The system of claim 10, wherein, at a time prior to committing a transaction, performing by a core processor in the plurality of core processors an operation to abort speculation in each remote computation with which it conflicts.

12. The system of claim 7, further comprising:

a concise record of certain cache lines recently read from and written to, wherein this record is used, on each cache coherence protocol interaction, to update per-core vectors, visible to software, that indicate conflicts with computations on other cores.