MOTHERBOARD HAVING TIME DELAY CIRCUIT FOR DELAYING PSON SIGNAL

• US 20120179930A1
• Filed: 03/17/2011
• Published: 07/12/2012
• Est. Priority Date: 01/08/2011
• Status: Active Grant

• Current Assignee: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. (Hon Hai Precision Industry Co., Ltd.), Hon Hai Precision Industry Co., Ltd.
• Original Assignee: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. (Hon Hai Precision Industry Co., Ltd.), Hon Hai Precision Industry Co., Ltd.
• Inventors: TONG, SONG-LIN, LUO, QI-YAN, CHEN, PENG
• Granted Patent: US 8,806,234 B2
• Time in Patent Office: Days
• US Class Current: 713/330
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations

Abstract

A motherboard includes a motherboard power supply connector and a time delay circuit. The motherboard power supply connector connects a power supply unit. The motherboard power supply connector has a power supply on pin and a power good pin. The power good pin is configured for receiving a power good signal from the power supply unit. The time delay circuit has an input terminal and an output terminal. The input terminal is configured for receiving a power supply on signal. The output terminal is connected to the power supply on pin and is configured for sending the power supply on signal to the power supply on pin after a time delay determined by the time delay circuit.

Claims

1. A motherboard, comprising:

a motherboard power supply connector configured for connecting a power supply unit, the motherboard power supply connector having a power supply on pin and a power good pin, the power good pin configured for receiving a power good signal from the power supply unit; and

a time delay circuit having an input terminal configured for receiving a power supply on signal and an output terminal, the output terminal connected to the power supply on pin and configured for sending the power supply on signal to the power supply on pin after a time delay determined by the time delay circuit.

2. The motherboard of claim 1, wherein the time delay circuit comprises a time delay chip, the time delay chip having an input pin configured for receiving the power supply on signal, and an output pin connected to the power supply on pin.

3. The motherboard of claim 2, wherein the time delay circuit further comprises a capacitor, and the time delay chip further comprises a reset period programming pin grounded via the capacitor, and a relationship between the value of the time delay T and the capacitance C of the capacitor is characterized by the following equation:

C=(T−

0.5×

0.001)×

175, where a unit of the capacitance C is nanofarad and a unit of the time delay T is second.

4. The motherboard of claim 2, wherein the time delay circuit comprises a first electrical switch, a control terminal of the first electrical switch is connected to the output pin, a first terminal of the first electrical switch is grounded, and a second terminal of the first electrical switch is connected to the output terminal of the time delay circuit.

5. The motherboard of claim 4, wherein the motherboard power supply connector comprises a second electrical switch, a control terminal of the second electrical switch is connected to the output terminal of the time delay circuit, a first terminal of the second electrical switch is grounded and a second terminal of the second electrical switch is connected to the power supply on pin.

6. The motherboard of claim 5, wherein the motherboard power supply connector further comprises a third electrical switch and a fourth electrical switch, a control terminal of the third electrical switch is connected to the power good pin, a first terminal of the third electrical switch is grounded, a second terminal of the third electrical switch is connected to a control terminal of the fourth electrical switch, a first terminal of the fourth electrical switch is grounded, a second terminal of the fourth electrical switch is connected to a resistor, the motherboard power supply connector configured for converting the power good signal into a system activation signal using the third electrical switch and the fourth electrical switch and outputting the system boot up signal via a node between the second terminal of the fourth electrical switch and the resistor.