METAL OXIDE SEMICONDUCTOR STRUCTURE AND PRODUCTION METHOD THEREOF

• US 20120181532A1
• Filed: 05/05/2011
• Published: 07/19/2012
• Est. Priority Date: 01/13/2011
• Status: Active Grant

• Current Assignee: E Ink Holdings Incorporated
• Original Assignee: E Ink Holdings Incorporated
• Inventors: HUANG, Chuan-I, LIN, Chin-Wen, HUANG, Chung-Chin, SHINN, Ted Hong
• Granted Patent: US 9,006,730 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A metal oxide semiconductor structure and a production method thereof, the structure including: a substrate; a gate electrode, deposited on the substrate; a gate insulation layer, deposited over the gate electrode and the substrate; an IGZO layer, deposited on the gate insulation layer and functioning as a channel; a source electrode, deposited on the gate insulation layer and being at one side of the IGZO layer; a drain electrode, deposited on the gate insulation layer and being at another side of the IGZO layer; a first passivation layer, deposited over the source electrode, the IGZO layer, and the drain electrode; a second passivation layer, deposited over the first passivation layer; and an opaque resin layer, deposited over the source electrode, the second passivation layer, and the drain electrode.

Claims

1. A metal oxide semiconductor structure, comprising:

a substrate;

a gate electrode, being made of metal and deposited on said substrate, for coupling to a gate driving signal;

a gate insulation layer, being an insulation layer deposited over said gate electrode and said substrate;

an IGZO layer, being an In—

Ga—

Zn—

O layer deposited on said gate insulation layer, for functioning as a channel;

a source electrode, being made of metal and deposited at one side of said IGZO layer, for coupling to a source driving signal;

a drain electrode, being made of metal and deposited at another side of said IGZO layer, for coupling to a pixel electrode;

a first passivation layer, being a first silicon compound layer deposited over said source electrode, said IGZO layer, and said drain electrode;

a second passivation layer, being a second silicon compound layer deposited over said first passivation layer; and

a resin layer, being an opaque resin layer deposited over said source electrode, said second passivation layer, and said drain electrode.

2. The metal oxide semiconductor structure as claim 1, wherein said substrate comprises glass or flexible plastics.

3. The metal oxide semiconductor structure as claim 2, wherein said gate electrode comprises Mo/Cr alloy or Al/Nd alloy.

4. The metal oxide semiconductor structure as claim 3, wherein said gate insulation layer has an upward bending portion and comprises a silicon oxide or a silicon nitride.

5. The metal oxide semiconductor structure as claim 4, wherein said IGZO layer has an upward bending portion.

6. The metal oxide semiconductor structure as claim 5, wherein said source electrode has a stair-stepping outline and comprises Mo/Cr alloy or Al/Nd alloy.

7. The metal oxide semiconductor structure as claim 6, wherein said drain electrode has a stair-stepping outline and comprises Mo/Cr alloy or Al/Nd alloy.

8. The metal oxide semiconductor structure as claim 7, wherein said first passivation layer has a downward bending portion and said first silicon compound layer comprises a silicon oxide.

9. The metal oxide semiconductor structure as claim 8, wherein said second passivation layer has a downward bending portion and said second silicon compound layer comprises a silicon nitride.

10. The metal oxide semiconductor structure as claim 9, wherein said resin layer is in black color.

11. The metal oxide semiconductor structure as claim 4, wherein said IGZO layer has a downward bending portion.

12. A method of making a metal oxide semiconductor structure, comprising the steps of:

depositing a gate electrode on a substrate;

depositing a gate insulation layer over said gate electrode and said substrate;

depositing an IGZO layer on said gate insulation layer, wherein said IGZO layer functions as a channel;

depositing a source electrode at one side of said IGZO layer;

depositing a drain electrode at another side of said IGZO layer;

depositing a first passivation layer over said source electrode, said IGZO layer, and said drain electrode;

depositing a second passivation layer over said first passivation layer; and

depositing an opaque resin layer over said source electrode, said second passivation layer, and said drain electrode.

13. The method of making a metal oxide semiconductor structure as claim 12, wherein said substrate comprises glass or flexible plastics, and said gate electrode comprises Mo/Cr alloy or Al/Nd alloy.

14. The method of making a metal oxide semiconductor structure as claim 13, wherein said gate insulation layer has an upward bending portion in the middle region and comprises a silicon oxide or a silicon nitride.

15. The method of making a metal oxide semiconductor structure as claim 14, wherein said IGZO layer has an upward bending portion.

16. The method of making a metal oxide semiconductor structure as claim 15, wherein said source electrode has a stair-stepping outline and comprises Mo/Cr alloy or Al/Nd alloy.

17. The method of making a metal oxide semiconductor structure as claim 16, wherein said drain electrode has a stair-stepping outline and comprises Mo/Cr alloy or Al/Nd alloy.

18. The method of making a metal oxide semiconductor structure as claim 17, wherein said first passivation layer has a downward bending portion and comprises a silicon oxide.

19. The method of making a metal oxide semiconductor structure as claim 18, wherein said second passivation layer has a downward bending portion and comprises a silicon nitride.

20. The method of making a metal oxide semiconductor structure as claim 19, wherein said opaque resin layer is in black color.

21. A method of making a metal oxide semiconductor structure, comprising the steps of:

depositing a gate electrode on a substrate;

depositing a gate insulation layer over said gate electrode and said substrate;

depositing a source electrode at one side of said gate insulation layer;

depositing a drain electrode at another side of said gate insulation layer;

depositing an IGZO layer over said source electrode, said gate insulation layer, and said drain electrode, wherein said IGZO layer functions as a channel;

depositing a first passivation layer over said source electrode, said IGZO layer, and said drain electrode;

depositing a second passivation layer over said first passivation layer; and

depositing an opaque resin layer over said source electrode, said second passivation layer, and said drain electrode.

22. The method of making a metal oxide semiconductor structure as claim 21, wherein said first passivation layer comprises a silicon oxide.

23. The method of making a metal oxide semiconductor structure as claim 22, wherein said second passivation layer comprises a silicon nitride.

24. The method of making a metal oxide semiconductor structure as claim 23, wherein said opaque resin layer is in black color.