Multi-Layer Single Crystal 3D Stackable Memory

• US 20120181654A1
• Filed: 08/31/2011
• Published: 07/19/2012
• Est. Priority Date: 01/19/2011
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting
• Granted Patent: US 8,486,791 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Technology is described herein for manufacturing a three-dimensional 3D stacked memory structure having multiple layers of single crystal silicon or other semiconductor. The multiple layers of single crystal semiconductor are suitable for implementing multiple levels of high performance memory cells.

Claims

1. A method for manufacturing a memory device, the method comprising:

bonding a first single crystal semiconductor body to a surface of a first layer of insulating material, and splitting the first single crystal semiconductor body on a plane generally parallel to the surface of the first layer of insulating material, leaving a first layer of single crystal semiconductor bonded on the first layer of insulating material;

forming a second layer of insulating material on the first layer of single crystal semiconductor material;

bonding a second single crystal semiconductor body to a surface of the second layer of insulating material, and splitting the second single crystal semiconductor body on a plane generally parallel to the surface of the second layer of insulating material, leaving a second layer of single crystal semiconductor bonded on the second layer of insulating material; and

processing the first and second layers of single crystal semiconductor layer to form a 3D memory array.

2. The method of claim 1, further comprising implanting ions to form a defect layer within the first single crystal semiconductor body prior to bonding to surface of the first layer of insulating material, and after bonding to the surface of the first layer of insulating material, splitting the substrate at the defect layer to leave the first layer of single crystal semiconductor material bonded on the first layer of insulating material.

3. The method of claim 2, wherein implanting ions comprises implanting hydrogen ions.

4. The method of claim 2, wherein splitting the first single crystal semiconductor body at the defect layer comprises annealing to induce the splitting at the defect layer.

5. The method of claim 1, wherein processing the first and second layers of single crystal semiconductor material includes:

etching the first and second layers of single crystal semiconductor material to define a plurality of stacks of single crystal semiconductor material strips separated by the insulating material;

forming a plurality of conductive lines overlying the plurality of stacks; and

forming memory elements adjacent the plurality of stacks, which establish a 3D array of memory cells accessible via the plurality of single crystal semiconductor material strips and the plurality of conductive lines.

6. The method of claim 5, wherein:

forming the plurality of conductive lines establishes a 3D array of interface regions at cross-points between surfaces of the single crystal semiconductor material strips and the plurality of conductive lines; and

the memory elements are formed in the interface regions.

7. The method of claim 6, wherein:

forming the memory elements comprises forming a memory layer on sides of single crystal semiconductor material strips in the plurality of stacks; and

forming the plurality of conductive lines over and having a surface conformal with the memory layer on the plurality of stacks.

8. The method of claim 7, wherein the memory layer comprises a layer of anti-fuse material.

9. The method of claim 7, wherein the memory layer includes a multilayer charge storage structure.

10. The method of claim 5, wherein the single crystal semiconductor material strips comprise a doped semiconductor material having a first conductivity type and the plurality of conductive lines comprise a doped semiconductor material having a second conductivity type establishing a p-n junction in said interface regions.

11. The method of claim 5, wherein the single crystal semiconductor material strips comprise a doped semiconductor so that the strips are arranged for operation of the memory cells as charge storage transistors.

12. The method of claim 1, wherein the second single crystal semiconductor body is a remaining portion of the first single crystal semiconductor body after leaving the first layer of single crystal semiconductor.

13. A method for manufacturing a memory device, the method comprising:

forming a plurality of stacked layers of single crystal semiconductor material, wherein forming each particular layer of single crystal semiconductor material in the plurality comprises bonding a single crystal semiconductor body to a layer of insulating material, and splitting the single crystal semiconductor body such that the particular layer of the single crystal semiconductor material remains on the layer of the insulating material;

etching the plurality of layers to define a plurality of stacks of single crystal semiconductor material strips;

forming a plurality of conductive lines overlying the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the single crystal semiconductor material strips and the plurality of conductive lines; and

forming memory elements in the interface regions, which establish a 3D array of memory cells accessible via the plurality of single crystal semiconductor material strips and the plurality of conductive lines.

14. A memory device manufactured by a method comprising:

bonding a first single crystal semiconductor body to a surface of a first layer of insulating material, and splitting the first single crystal semiconductor body on a plane generally parallel to the surface of the first layer of insulating material, leaving a first layer of single crystal semiconductor bonded on the first layer of insulating material;

forming a second layer of insulating material on the first layer of single crystal semiconductor material;

bonding a second single crystal semiconductor body to a surface of the second layer of insulating material, and splitting the second single crystal semiconductor body on a plane generally parallel to the surface of the second layer of insulating material, leaving a second layer of single crystal semiconductor bonded on the second layer of insulating material; and

processing the first and second layers of single crystal semiconductor layer to form a 3D memory array.

15. The memory device of claim 14, wherein the method further comprises implanting ions to form a defect layer within the first single crystal semiconductor body prior to bonding to surface of the first layer of insulating material, and after bonding to the surface of the first layer of insulating material, splitting the substrate at the defect layer to leave the first layer of single crystal semiconductor material bonded on the first layer of insulating material.

16. The memory device of claim 15, wherein implanting ions comprises implanting hydrogen ions.

17. The memory device of claim 15, wherein splitting the first single crystal semiconductor body at the defect layer comprises annealing to induce the splitting at the defect layer.

18. The memory device of claim 14, wherein processing the first and second layers of single crystal semiconductor material includes:

etching the first and second layers of single crystal semiconductor material to define a plurality of stacks of single crystal semiconductor material strips separated by the insulating material;

forming a plurality of conductive lines overlying the plurality of stacks; and

forming memory elements adjacent the plurality of stacks, which establish a 3D array of memory cells accessible via the plurality of single crystal semiconductor material strips and the plurality of conductive lines.

19. The memory device of claim 18, wherein:

forming the plurality of conductive lines establishes a 3D array of interface regions at cross-points between surfaces of the single crystal semiconductor material strips and the plurality of conductive lines; and

the memory elements are formed in the interface regions.

20. The memory device of claim 19, wherein:

forming the memory elements comprises forming a memory layer on sides of single crystal semiconductor material strips in the plurality of stacks; and

forming the plurality of conductive lines over and having a surface conformal with the memory layer on the plurality of stacks.

21. The memory device of claim 20, wherein the memory layer comprises a layer of anti-fuse material.

22. The memory device of claim 20, wherein the memory layer includes a multilayer charge storage structure.

23. The memory device of claim 18, wherein the single crystal semiconductor material strips comprise a doped semiconductor material having a first conductivity type and the plurality of conductive lines comprise a doped semiconductor material having a second conductivity type establishing a p-n junction in said interface regions.

24. The memory device of claim 18, wherein the single crystal semiconductor material strips comprise a doped semiconductor so that the strips are arranged for operation of the memory cells as charge storage transistors.

25. The memory device of claim 14, wherein the second single crystal semiconductor body is a remaining portion of the first single crystal semiconductor body after leaving the first layer of single crystal semiconductor.