POWER SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
First Claim
1. A power semiconductor package structure, comprising:
- a carrier;
a first power chip having a first surface and a second surface opposing to the first surface, wherein a first control electrode and a first main power electrode are disposed on the first surface, a second main power electrode is disposed on the second surface, and the second surface is disposed on the carrier and electrically connected to the carrier through the second main power electrode;
a second power chip having a third surface and a fourth surface opposing to the third surface, wherein a third main power electrode is disposed on the third surface, a fourth main power electrode is disposed on the fourth surface, and the fourth surface is disposed on the first power chip;
a first conductive sheet electrically connected to the first main power electrode and the fourth main power electrode;
a second conductive sheet electrically connected to the third main power electrode; and
a third conductive sheet electrically connected to the first control electrode;
wherein, at least a part of the first control electrode is non-covered by the second power chip along a projection direction perpendicular to the carrier.
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Accused Products
Abstract
A power semiconductor package structure includes a carrier, a first power chip, a second power chip, a first conductive sheet, a second conductive sheet and a third conductive sheet. The first power chip has a first surface and a second surface opposing to the first surface. A first control electrode and a first main power electrode are disposed on the first surface, and a second main power electrode is disposed on the second surface. The second surface is disposed on the carrier, and electrically connected to the carrier through the second main power electrode. The second power chip has a third surface and a fourth surface opposing to the third surface. A third main power electrode is disposed on the third surface, and a fourth main power electrode is disposed on the fourth surface. The fourth surface is disposed on the first power chip. The first conductive sheet is electrically connected to the first main power electrode and the fourth main power electrode. The second conductive sheet is electrically connected to the third main power electrode. The third conductive sheet is electrically connected to the first control electrode. At least a part of the first control electrode is non-covered by the second power chip along a projection direction, which is perpendicular to the carrier.
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Citations
21 Claims
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1. A power semiconductor package structure, comprising:
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a carrier; a first power chip having a first surface and a second surface opposing to the first surface, wherein a first control electrode and a first main power electrode are disposed on the first surface, a second main power electrode is disposed on the second surface, and the second surface is disposed on the carrier and electrically connected to the carrier through the second main power electrode; a second power chip having a third surface and a fourth surface opposing to the third surface, wherein a third main power electrode is disposed on the third surface, a fourth main power electrode is disposed on the fourth surface, and the fourth surface is disposed on the first power chip; a first conductive sheet electrically connected to the first main power electrode and the fourth main power electrode; a second conductive sheet electrically connected to the third main power electrode; and a third conductive sheet electrically connected to the first control electrode; wherein, at least a part of the first control electrode is non-covered by the second power chip along a projection direction perpendicular to the carrier. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 13, 14)
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2. A power semiconductor package structure, comprising:
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a carrier; a first power chip having a first surface and a second surface opposing to the first surface, wherein a first control electrode and a first main power electrode are disposed on the first surface, a second main power electrode is disposed on the second surface, and the second surface is disposed on the carrier and electrically connected to the carrier through the second main power electrode; a second power chip having a third surface and a fourth surface opposing to the third surface, wherein a third main power electrode is disposed on the third surface, a fourth main power electrode is disposed on the fourth surface, and the fourth surface is disposed on the first power chip; a first conductive sheet electrically connected to the first main power electrode and the fourth main power electrode; and a second conductive sheet electrically connected to the third main power electrode; wherein, the dimension of the second power chip is not smaller than that of the first power chip, and at least a part of the first control electrode is non-covered by the second power chip along a projection direction perpendicular to the carrier. - View Dependent Claims (10, 11, 12, 15, 16)
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17. A manufacturing method of a power semiconductor package structure, comprising steps of
disposing a first power chip on a carrier, wherein the first power chip has a first control electrode; -
disposing a first conductive sheet on the first power chip; disposing a second power chip on the first conductive sheet, wherein at least a part of the first control electrode is non-covered by the second power chip along a projection direction perpendicular to the carrier; disposing a second conductive sheet on the second power chip; disposing a third conductive sheet to electrically connecting with the first control electrode of the first power chip; disposing a fourth conductive sheet to electrically connecting with the second power chip; and disposing a molding compound to cover the first power chip and the second power chip. - View Dependent Claims (18, 19, 20, 21)
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Specification