Semiconductor Device and Method of Manufacture Thereof

• US 20120181874A1
• Filed: 01/18/2011
• Published: 07/19/2012
• Est. Priority Date: 01/18/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Wahl, Uwe, Knott, Bernhard, Hammer, Markus, Strasser, Andreas, Willkofer, Stefan
• Granted Patent: US 8,614,616 B2
• Time in Patent Office: Days
• US Class Current: 307/104
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19102 : in a stacked assembly with the semiconductor or solid state device
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: Y10T 29/4902 : Electromagnet, transformer or inductor

Abstract

A semiconductor device, a method of manufacturing a semiconductor device and a method for transmitting a signal are disclosed. In accordance with an embodiment of the present invention, the semiconductor device comprises a first semiconductor chip comprising a first coil, a second semiconductor chip comprising a second coil inductively coupled to the first coil, and an isolating intermediate layer between the first semiconductor chip and the second semiconductor chip.

Claims

1. A semiconductor device comprising:

a first semiconductor chip comprising a first coil;

a second semiconductor chip comprising a second coil inductively coupled to the first coil; and

an isolating intermediate film between the first semiconductor chip and the second semiconductor chip.

2. The semiconductor device according to claim 1, wherein the isolating intermediate film is a double sided adhesive film having a dielectric strength between about 60 kV/mm to about 100 kV/mm.

3. The semiconductor device according to claim 1, wherein the isolating intermediate film is an attach paste having a dielectric strength between about 60 KV/mm to about 100 kV/mm.

4. The semiconductor device according to claim 1, wherein the isolating intermediate film comprises a thickness of about 20 μ

m to about 500 μ

m.

5. The semiconductor device according to claim 1, wherein the first semiconductor chip comprises an integrated circuit and wherein the second semiconductor chip consists of a second pad, the second coil and an electrical connection between the second pad and the second coil.

6. The semiconductor device according to claim 1, wherein the semiconductor device further comprises a lead frame, wherein a first pad of the first semiconductor chip is bonded to the lead frame and where a second pad of the second semiconductor chip is bonded to the lead frame.

7. The semiconductor device according to claim 1, wherein the first coil of the first semiconductor chip and the second coil of the second semiconductor chip form a transformer.

8. A method of manufacturing a semiconductor device, the method comprising:

manufacturing a first semiconductor chip comprising a first coil;

manufacturing a second semiconductor chip comprising a second coil;

aligning the first semiconductor chip with the second semiconductor chip so that the first coil is arranged opposite to the second coil; and

bonding the first semiconductor chip with the second semiconductor chip.

9. The method according to claim 8, wherein bonding the first semiconductor chip with the second semiconductor chip comprises bonding the first semiconductor chip with the second semiconductor chip via an intermediate isolation film.

10. The method according to claim 9, wherein the intermediate isolation film comprises a thickness of about 20 μ

m to about 500 μ

m.

11. The method according to claim 9, wherein the intermediate isolation film is a double sided adhesive film having a dielectric strength between about 60 kV/mm to about 100 kV/mm.

12. The method according to claim 9, wherein the intermediate isolation film is an attach paste having a dielectric strength between about 60 KV/mm to about 100 kV/mm.

13. The method according to claim 8, wherein aligning the first semiconductor chip with the second semiconductor chip comprises placing the first semiconductor chip face-to-face to the second semiconductor chip.

14. The method according to claim 8, further comprising thinning a substrate of the second semiconductor chip to a thickness of about 60 μ

m to about 300 μ

m.

15. The method according to claim 14, further comprising etching a through-via in the substrate of the second semiconductor chip.

16. The method according to claim 15, further comprising electrically connecting a connection pad of the second semiconductor chip through the through substrate via with a lead frame.

17. A method for transmitting a signal, the method comprising:

receiving a signal at a first connection pad of a first semiconductor chip;

transforming the signal from a first coil on the first semiconductor chip to a second coil on a semiconductor chip; and

sending the signal via a second connection pad of the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip together form a transformer.

18. The method according to claim 17, wherein the first semiconductor chip and the second semiconductor chip are galvanically separated.

19. The method according to claim 17, wherein the first semiconductor chip and the second semiconductor chip are attached to each other with an adhesive film or an attach paste having a dielectric strength between about 60 kV/mm to about 100 kV/mm.

20. The method according to claim 19, wherein the adhesive film or the attach paste comprises a thickness of about 20 μ

m to about 500 μ

m.