MONITORING NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) AND/OR POSITIVE BIAS TEMPERATURE INSTABILITY (PBTI)

• US 20120182079A1
• Filed: 01/19/2011
• Published: 07/19/2012
• Est. Priority Date: 01/19/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rao, Rahul M., Kim, Jae-Joon
• Granted Patent: US 8,456,247 B2
• Time in Patent Office: Days
• US Class Current: 331/57
• CPC Class Codes: G06F 2119/08 Thermal analysis or thermal optimisation
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

A ring oscillator circuit for measurement of negative bias temperature instability effect and/or positive bias temperature instability effect includes a ring oscillator having first and second rails, and an odd number (at least 3) of repeating circuit structures. Each of the repeating circuit structures in turn includes an input terminal and an output terminal; a first p-type transistor having a gate, a first drain-source terminal coupled to the first rail, and a second drain source terminal selectively coupled to the output terminal; a first n-type transistor having a gate, a first drain-source terminal coupled to the second rail, and a second drain source terminal selectively coupled to the output terminal; and repeating-circuit-structure control circuitry. The ring oscillator circuit also includes a voltage supply and control block.

Claims

1. A ring oscillator circuit for measurement of at least one of negative bias temperature instability effect and positive bias temperature instability effect, said circuit comprising:

a ring oscillator comprising first and second rails, and an odd number of repeating circuit structures, said odd number being at least three, each of said repeating circuit structures comprising;

an input terminal and an output terminal;

a first p-type transistor having a gate, a first drain-source terminal coupled to said first rail, and a second drain source terminal selectively coupled to said output terminal;

a first n-type transistor having a gate, a first drain-source terminal coupled to said second rail, and a second drain source terminal selectively coupled to said output terminal; and

repeating-circuit-structure control circuitry;

wherein each of said repeating circuit structures has its output terminal connected to said input terminal of an immediately adjacent one of said repeating circuit structures; and

a voltage supply and control block coupled to said ring oscillator and configured to cooperate with said repeating-circuit-structure control circuitry such that;

during a negative bias temperature instability effect direct current stress mode, said gates of said first n-type transistors are grounded to turn them off, a stress voltage differential is applied between said first rail and said gates of said first p-type transistors to stress them, and said second rail is grounded;

during a positive bias temperature instability effect direct current stress mode, said gates of said first p-type transistors are held at a nominal supply voltage to turn them off, a stress voltage differential is applied between said second rail and said gates of said first n-type transistors to stress them, and said first rail is held at said nominal supply voltage; and

during a measurement mode, said nominal supply voltage is applied to said first rail and a ground to said second rail, and said second drain source terminals of said first n-type transistors and said first p-type transistors are coupled to said output terminals, such that each of said repeating circuit structures functions as an inverter.

2. The circuit of claim 1, wherein:

said ring oscillator further comprises a p-stress enable terminal coupled to said gates of said first p-type transistors, an n-stress enable terminal coupled to said gates of said first n-type transistors, a p-bias terminal, and an n-bias terminal;

said repeating-circuit-structure control circuitry comprises, for each of said repeating circuit structures;

a second p-type transistor having a gate coupled to said input terminal, a first drain-source terminal coupled to said second drain source terminal of said first p-type transistor, and a second drain source terminal coupled to said output terminal;

a third p-type transistor having a gate coupled to said p-bias terminal, a first drain-source terminal coupled to said first rail, and a second drain source terminal coupled to said output terminal;

a second n-type transistor having a gate coupled to said input terminal, a first drain-source terminal coupled to said second drain source terminal of said first n-type transistor, and a second drain source terminal coupled to said output terminal; and

a third n-type transistor having a gate coupled to said n-bias terminal, a first drain-source terminal coupled to said second rail, and a second drain source terminal coupled to said output terminal; and

said voltage supply and control block is further configured to apply;

during said negative bias temperature instability effect direct current stress mode, said ground to said p-bias and n-bias terminals;

during said positive bias temperature instability effect direct current stress mode, said nominal supply voltage to said p-bias and n-bias terminals.

3. The circuit of claim 2, wherein said voltage supply and control block is further configured such that:

during a negative bias temperature instability effect alternating current stress mode, said gates of said first n-type transistors are grounded to turn them off, a pulsed AC stress voltage differential is applied between said first rail and said gates of said first p-type transistors to stress them, and said second rail is grounded; and

during a positive bias temperature instability effect alternating current stress mode, said gates of said first p-type transistors are held at a nominal supply voltage to turn them off, a pulsed AC stress voltage differential is applied between said second rail and said gates of said first n-type transistors to stress them, and said first rail is held at said nominal supply voltage.

4. The circuit of claim 3, wherein said voltage supply and control block is implemented in hardware.

5. The circuit of claim 3, wherein said voltage supply and control block is implemented at least partially in software, embodied in a computer readable storage medium, executing on at least one hardware processor.

6. The circuit of claim 3, further comprising:

a multiplexer having a first input configured for connection to an on-chip voltage controlled oscillator and a second input configured for connection to an external stress, and having an output;

a first divider having an input coupled to said output of said multiplexer and an output configured for interconnection with an oscilloscope;

a level converter coupled to said output of said multiplexer and an output coupled to said ring oscillator; and

a second divider having an input coupled to said output of said multiplexer and an output configured for interconnection with an oscilloscope.

7. A method comprising the steps of:

providing a ring oscillator comprising first and second rails, and an odd number of repeating circuit structures, said odd number being at least three, each of said repeating circuit structures comprising;

an input terminal and an output terminal;

a first p-type transistor having a gate, a first drain-source terminal coupled to said first rail, and a second drain source terminal selectively coupled to said output terminal; and

a first n-type transistor having a gate, a first drain-source terminal coupled to said second rail, and a second drain source terminal selectively coupled to said output terminal;

wherein each of said repeating circuit structures has its output terminal connected to said input terminal of an immediately adjacent one of said repeating circuit structures;

during a negative bias temperature instability effect direct current stress mode, grounding said gates of said first n-type transistors to turn them off, applying a stress voltage differential between said first rail and said gates of said first p-type transistors to stress them, and grounding said second rail;

during a positive bias temperature instability effect direct current stress mode, holding said gates of said first p-type transistors at a nominal supply voltage to turn them off, applying a stress voltage differential between said second rail and said gates of said first n-type transistors to stress them, and holding said first rail at said nominal supply voltage; and

during a measurement mode, applying said nominal supply voltage to said first rail and a ground to said second rail, and coupling said second drain source terminals of said first n-type transistors and said first p-type transistors to said output terminals, such that each of said repeating circuit structures functions as an inverter.

8. The method of claim 7, wherein:

said ring oscillator further comprises;

a p-stress enable terminal coupled to said gates of said first p-type transistors, an n-stress enable terminal coupled to said gates of said first n-type transistors, a p-bias terminal, and an n-bias terminal;

for each of said repeating circuit structures;

a second p-type transistor having a gate coupled to said input terminal, a first drain-source terminal coupled to said second drain source terminal of said first p-type transistor, and a second drain source terminal coupled to said output terminal;

a third p-type transistor having a gate coupled to said p-bias terminal, a first drain-source terminal coupled to said first rail, and a second drain source terminal coupled to said output terminal;

a second n-type transistor having a gate coupled to said input terminal, a first drain-source terminal coupled to said second drain source terminal of said first n-type transistor, and a second drain source terminal coupled to said output terminal; and

a third n-type transistor having a gate coupled to said n-bias terminal, a first drain-source terminal coupled to said second rail, and a second drain source terminal coupled to said output terminal;

further comprising;

during said negative bias temperature instability effect direct current stress mode, applying said ground to said p-bias and n-bias terminals;

during said positive bias temperature instability effect direct current stress mode, applying said nominal supply voltage to said p-bias and n-bias terminals.

9. The method of claim 8, further comprising:

during a negative bias temperature instability effect alternating current stress mode, grounding said gates of said first n-type transistors to turn them off, applying a pulsed AC stress voltage differential between said first rail and said gates of said first p-type transistors to stress them, and grounding said second rail; and

during a positive bias temperature instability effect alternating current stress mode, holding said gates of said first p-type transistors at a nominal supply voltage to turn them off, applying a pulsed AC stress voltage differential between said second rail and said gates of said first n-type transistors to stress them, and holding said first rail at said nominal supply voltage.

10. The method of claim 8, further comprising:

prior to said positive bias temperature instability effect direct current stress mode, sweeping voltage at said n-stress enable terminal for a predetermined range of interest and recording corresponding ring oscillator frequency under pre-stress conditions;

subsequent to said positive bias temperature instability effect direct current stress mode, maintaining said n-stress enable terminal at said nominal supply voltage and recording corresponding ring oscillator frequency under post-stress conditions; and

determining a value of threshold voltage degradation due to said positive bias temperature instability effect by subtracting said nominal supply voltage from that value of said swept voltage at said n-stress enable terminal which corresponds to a value of said corresponding ring oscillator frequency under pre-stress conditions that matches said ring oscillator frequency under post-stress conditions.

11. The method of claim 8, further comprising:

prior to said negative bias temperature instability effect direct current stress mode, sweeping voltage at said p-stress enable terminal for a predetermined range of interest and recording corresponding ring oscillator frequency under pre-stress conditions;

subsequent to said negative bias temperature instability effect direct current stress mode, maintaining said p-stress enable terminal at ground and recording corresponding ring oscillator frequency under post-stress conditions; and

determining a value of threshold voltage degradation due to said negative bias temperature instability effect by subtracting said ground from that value of said swept voltage at said p-stress enable terminal which corresponds to a value of said corresponding ring oscillator frequency under pre-stress conditions that matches said ring oscillator frequency under post-stress conditions.

12. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, said design structure comprising a ring oscillator circuit for measurement of at least one of negative bias temperature instability effect and positive bias temperature instability effect, said circuit comprising:

a ring oscillator comprising first and second rails, and an odd number of repeating circuit structures, said odd number being at least three, each of said repeating circuit structures comprising;

an input terminal and an output terminal;

a first p-type transistor having a gate, a first drain-source terminal coupled to said first rail, and a second drain source terminal selectively coupled to said output terminal;

a first n-type transistor having a gate, a first drain-source terminal coupled to said second rail, and a second drain source terminal selectively coupled to said output terminal; and

repeating-circuit-structure control circuitry;

wherein each of said repeating circuit structures has its output terminal connected to said input terminal of an immediately adjacent one of said repeating circuit structures; and

a voltage supply and control block coupled to said ring oscillator and configured to cooperate with said repeating-circuit-structure control circuitry such that;

during a negative bias temperature instability effect direct current stress mode, said gates of said first n-type transistors are grounded to turn them off, a stress voltage differential is applied between said first rail and said gates of said first p-type transistors to stress them, and said second rail is grounded;

during a positive bias temperature instability effect direct current stress mode, said gates of said first p-type transistors are held at a nominal supply voltage to turn them off, a stress voltage differential is applied between said second rail and said gates of said first n-type transistors to stress them, and said first rail is held at said nominal supply voltage; and

during a measurement mode, said nominal supply voltage is applied to said first rail and a ground to said second rail, and said second drain source terminals of said first n-type transistors and said first p-type transistors are coupled to said output terminals, such that each of said repeating circuit structures functions as an inverter.

13. The design structure of claim 12, wherein said circuit further comprises:

said ring oscillator further comprises a p-stress enable terminal coupled to said gates of said first p-type transistors, an n-stress enable terminal coupled to said gates of said first n-type transistors, a p-bias terminal, and an n-bias terminal;

said repeating-circuit-structure control circuitry comprises, for each of said repeating circuit structures;

a second p-type transistor having a gate coupled to said input terminal, a first drain-source terminal coupled to said second drain source terminal of said first p-type transistor, and a second drain source terminal coupled to said output terminal;

a third p-type transistor having a gate coupled to said p-bias terminal, a first drain-source terminal coupled to said first rail, and a second drain source terminal coupled to said output terminal;

a second n-type transistor having a gate coupled to said input terminal, a first drain-source terminal coupled to said second drain source terminal of said first n-type transistor, and a second drain source terminal coupled to said output terminal; and

a third n-type transistor having a gate coupled to said n-bias terminal, a first drain-source terminal coupled to said second rail, and a second drain source terminal coupled to said output terminal; and

said voltage supply and control block is further configured to apply;

during said negative bias temperature instability effect direct current stress mode, said ground to said p-bias and n-bias terminals;

during said positive bias temperature instability effect direct current stress mode, said nominal supply voltage to said p-bias and n-bias terminals.

14. The design structure of claim 13, wherein said voltage supply and control block of said circuit is further configured such that:

during a negative bias temperature instability effect alternating current stress mode, said gates of said first n-type transistors are grounded to turn them off, a pulsed AC stress voltage differential is applied between said first rail and said gates of said first p-type transistors to stress them, and said second rail is grounded; and

during a positive bias temperature instability effect alternating current stress mode, said gates of said first p-type transistors are held at a nominal supply voltage to turn them off, a pulsed AC stress voltage differential is applied between said second rail and said gates of said first n-type transistors to stress them, and said first rail is held at said nominal supply voltage.

15. The design structure of claim 14, wherein said voltage supply and control block of said circuit is implemented in hardware.

16. The design structure of claim 14, wherein said circuit further comprises:

a multiplexer having a first input configured for connection to an on-chip voltage controlled oscillator and a second input configured for connection to an external stress, and having an output;

a first divider having an input coupled to said output of said multiplexer and an output configured for interconnection with an oscilloscope;

a level converter coupled to said output of said multiplexer and an output coupled to said ring oscillator; and

a second divider having an input coupled to said output of said multiplexer and an output configured for interconnection with an oscilloscope.