BUFFER TO DRIVE REFERENCE VOLTAGE

• US 20120182167A1
• Filed: 01/14/2011
• Published: 07/19/2012
• Est. Priority Date: 01/14/2011
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: WAKIMOTO, Tsutomu
• Granted Patent: US 8,390,491 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 1/342 in field-effect transistor amplifiers
• CPC Class Codes: H03F 2200/405 the output amplifying stage of an amplifier comprising more than three power stages
• CPC Class Codes: H03F 3/345 with field-effect devices H03F3/347 takes precedence

Abstract

Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.

Claims

1. An amplifier circuit comprising:

a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain;

a second transistor to form an active load of the first transistor, the second transistor having its drain and gate coupled to the drain of the first transistor;

a third transistor to form a current mirror with the second transistor;

a fourth transistor to form an active load of the third transistor; and

a fifth transistor to form a current mirror with the fourth transistor, the fifth transistor being connected to the drain of the second transistor.

2. The amplifier circuit of claim 1, wherein a device ratio between the second transistor and the fifth transistor is 1:

K1 with K1 being a number less than one.

3. The amplifier circuit of claim 1, further comprising a sixth transistor as part of a transconductance (Gm) stage, the gate of the sixth transistor being coupled to the gate of the second transistor, and the second transistor and sixth transistor forming a current mirror.

4. The amplifier circuit of claim 3, further comprising a first and second current sources, wherein the current flowing through the sixth transistor are divided between the first and second current sources.

5. The amplifier circuit of claim 4, wherein a device ratio between the second transistor and the sixth transistor is 1:

K2 with K2 being a number larger than one, the first current source providing a bias current for the sixth transistor and the second current source providing a load current for a following circuit.

6. The amplifier circuit of claim 1, further comprising a bias current source to provide a bias current to the first transistor.

7. The amplifier circuit of claim 6, wherein the bias current source is a Gm-constant bias circuit.

8. The amplifier circuit of claim 1, further comprising:

a plurality of differential amplifiers chained together to generate the input voltage signal, and

a Gm stage that comprises a sixth transistor, the gate of the sixth transistor being coupled to the gate of the second transistor, and the second transistor and sixth transistor forming a current mirror,

wherein the Gm stage generates an output signal at the drain of the sixth transistor, the first differential amplifier has a first input terminal coupled to a reference voltage and a second input terminal coupled to the output signal at the drain of the sixth transistor via a feedback loop.

9. The amplifier circuit of claim 8, wherein the reference voltage is a bandgap reference voltage and the integrated circuit provides a reference buffer:

10. A reference buffer circuit comprising:

a plurality of cascaded amplifiers; and

a transconductance (Gm) stage coupled to a last amplifier of the plurality cascaded amplifiers, wherein the last amplifier comprises;

a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain, the input voltage signal being generated by a preceding differential amplifier;

a second transistor to form an active load of the first transistor, the second transistor having its drain and gate coupled to the drain of the first transistor;

a third transistor to form a current mirror with the second transistor;

a fourth transistor to form an active load of the third transistor; and

a fifth transistor to form a current mirror with the fourth transistor, the fifth transistor being connected to the drain of the second transistor; and

the Gm stage comprises;

a sixth transistor, the gate of the sixth transistor being coupled to the gate of the second transistor, and the second transistor and sixth transistor forming a current mirror, and

a first and second current sources, wherein the current flowing through the sixth transistor are divided between a bias current and a load current, the Gm stage generating an output signal at the drain of the sixth transistor, the first amplifier of the plurality of stages of amplifiers has a first input terminal coupled to a reference voltage and a second input terminal coupled to the output signal at the drain of the sixth transistor via a feedback loop.

11. The reference buffer circuit of claim 10, wherein a device ratio between the second transistor and the fifth transistor is 1:

K1 with K1 being a number less than one.

12. The reference buffer circuit of claim 10, wherein a device ratio between the second transistor and the sixth transistor is 1:

K2 with K2 being a number larger than one.

13. The reference buffer circuit of claim 10, further comprising a bias current source to provide a bias current to the first transistor.

14. The reference buffer circuit of claim 13, wherein the bias current source is a Gm-constant bias circuit.

15. A multichannel analog-to-digital converter (ADC) circuit comprising:

a plurality of successive approximation register analog-to-digital converters (SAR ADCs);

a capacitor to supply pulse current to the SAR ADCs; and

a reference buffer to supply average current to the external capacitor, the reference buffer comprising;

a plurality of cascaded amplifiers; and

a transconductance (Gm) stage coupled to a last amplifier of the plurality of cascaded amplifiers, wherein the last amplifier comprises;

a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain, the input voltage signal being generated by a preceding differential amplifier;

a second transistor to form an active load of the first transistor, the second transistor having its drain and gate coupled to the drain of the first transistor;

a third transistor to form a current mirror with the second transistor;

a fourth transistor to form an active load of the third transistor; and

a fifth transistor to form a current mirror with the fourth transistor, the fifth transistor being connected to the drain of the second transistor; and

the Gm stage comprises;

a sixth transistor, the gate of the sixth transistor being coupled to the gate of the second transistor, and the second transistor and sixth transistor forming a current mirror, and

a first and second current sources, wherein the current flowing through the sixth transistor are divided between a bias current and a load current, the Gm stage generating an output signal at the drain of the sixth transistor, the first amplifier of the plurality of stages of amplifiers has a first input terminal coupled to a reference voltage and a second input terminal coupled to the output signal at the drain of the sixth transistor via a feedback loop

16. The multichannel ADC circuit of claim 15, wherein a device ratio between the second transistor and the fifth transistor is 1:

K1 with K1 being a number less than one.

17. The multichannel ADC circuit of claim 15, wherein a device ratio between the second transistor and the sixth transistor is 1:

K2 with K2 being a number larger than one.

18. The multichannel ADC circuit of claim 15, further comprising a bias current source to provide a bias current to the first transistor.

19. The multichannel ADC circuit of claim 18, wherein the bias current source is a Gm-constant bias circuit.

20. The multichannel ADC circuit of claim 15, wherein the reference voltage is a bandgap reference voltage.