Systems and Methods for Reduced Format Data Processing
First Claim
1. A data processing circuit, the data processing circuit comprising:
- an analog front end circuit operable to receive an analog signal and to provide a series of digital samples corresponding to the analog signal;
a cosine component calculation circuit operable to calculate a cosine component from the series of digital samples;
a sine component calculation circuit operable to calculate a sine component from the series of digital samples; and
a zero phase start calculation circuit operable to provide a phase select output to a location detection circuit.
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Abstract
Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier circuit, an analog to digital conversion circuit, a cosine component calculation circuit, a sine calculation circuit, and a zero gain start calculation circuit. The variable gain amplifier circuit is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The analog to digital conversion circuit is operable to convert the amplified output to a corresponding series of digital samples. The cosine component calculation circuit is operable to calculate a cosine component from the series of digital samples, and the sine component calculation circuit operable to calculate a sine component from the series of digital samples. The zero gain start calculation circuit is operable to calculate a raw gain error value based on the cosine component and the sine component, where the gain feedback value is derived from the raw gain error value.
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Citations
25 Claims
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1. A data processing circuit, the data processing circuit comprising:
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an analog front end circuit operable to receive an analog signal and to provide a series of digital samples corresponding to the analog signal; a cosine component calculation circuit operable to calculate a cosine component from the series of digital samples; a sine component calculation circuit operable to calculate a sine component from the series of digital samples; and a zero phase start calculation circuit operable to provide a phase select output to a location detection circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for data processing, the method comprising:
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receiving an analog signal, wherein the analog signal includes a repeating signal; converting the analog signal to a series of digital samples synchronous to a sampling clock; performing a discrete Fourier transform of a first portion of the series of digital samples to yield a first sine component and a first cosine component; performing a discrete Fourier transform of a second portion of the series of digital samples to yield a second sine component and a second cosine component; performing a discrete Fourier transform of a third portion of the series of digital samples to yield a third sine component and a third cosine component; calculating a frequency error value based at least in part on the first sine component, the second sine component, the first cosine component and the second cosine component; adjusting the sampling clock based at least in part on the frequency error value; selecting a best phase based at least in part on the third sine component and the third cosine component; and performing a pattern detection using the best phase, wherein the pattern detection is performed in parallel with adjusting the sampling clock. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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23. A data storage device, the data storage device comprising:
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a storage medium operable to maintain information; a read head disposed in relation to the storage medium and operable to sense the information and to provide an analog signal corresponding to the information, wherein the information includes a repeating signal; a read circuit comprising; a variable gain amplifier circuit operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output; an analog to digital conversion circuit operable to convert the amplified output to a corresponding series of digital samples synchronous to a sampling clock; a cosine component calculation circuit operable to calculate a cosine component from the series of digital samples; a sine component calculation circuit operable to calculate a sine component from the series of digital samples; a zero gain start calculation circuit operable to calculate a raw gain error value based on the cosine component and the sine component, where the gain feedback value is derived from the raw gain error value; a first zero phase start circuit operable to calculate a first zero phase start value based upon a first portion of the series of digital samples, and to calculate a second zero phase start value based upon a second portion of the series of digital samples; a frequency error estimation circuit, wherein the frequency error estimation circuit calculates a frequency error value based at least in part on the first zero phase start value and the second zero phase start value; a clock generation circuit operable to generate the sampling clock base at least in part on the frequency error value; a second zero phase start circuit operable to calculate a third zero phase start value based upon a third portion of the series of digital samples; and a location detection circuit operable to detect a defined pattern using a phase selected based upon the third zero phase start value, wherein the location detection circuit operates in parallel to the frequency error estimation circuit. - View Dependent Claims (24, 25)
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Specification