SEMICONDUCTOR MEMORY DEVICE

• US 20120182779A1
• Filed: 01/17/2012
• Published: 07/19/2012
• Est. Priority Date: 01/17/2011
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: FUKUDA, Ryo
• Application Number:
  US13/351,737
• Publication Number:
  US 20120182779A1
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

According to one embodiment, a nonvolatile memory device includes a substrate, an interconnect layer, a memory layer, a circuit layer, first and second contact interconnects. The interconnect layer is provided on the substrate and includes first and second interconnects. The memory layer is provided between the substrate and the interconnect layer and includes first and second memory cell array units. The first and second memory cell array units include a plurality of memory cells. The circuit layer is provided between the memory layer and the substrate and includes a first circuit unit. The first contact interconnect is provided between the first and second memory cell array units and electrically connects one end of the first circuit unit to the first interconnect. The second contact interconnect electrically connects a second end of the first circuit unit different from the first end to the second interconnect.

Claims

1. A nonvolatile memory device comprising:

a substrate having a major surface;

an interconnect layer provided on the major surface, the interconnect layer including;

a first interconnect extending along a first direction parallel to the major surface; and

a second interconnect;

a memory layer provided between the substrate and the interconnect layer, the memory layer including;

a first memory cell array unit including a plurality of memory cells electrically connected to the first interconnect; and

a second memory cell array unit juxtaposed to the first memory cell array unit along the first direction and including a plurality of memory cells electrically connected to the first interconnect;

a circuit layer provided between the memory layer and the substrate and including a first circuit unit;

a first contact interconnect extending along a second direction from the substrate toward the interconnect layer between the first memory cell array unit and the second memory cell array unit and electrically connecting one end of the first circuit unit to the first interconnect; and

a second contact interconnect extending along the second direction on a opposite side of the first memory cell array unit to the first contact interconnect and electrically connecting a second end of the first circuit unit different from the first end to the second interconnect.

2. The device according to claim 1, wherein the first circuit unit includes a sensing amplifier circuit configured to detect electrical characteristics of the plurality of memory cells included in the first memory cell array unit and the plurality of memory cells included in the second memory cell array unit.

3. The device according to claim 2, wherein the first circuit unit includes a latch, which is connected to the sensing amplifier circuit.

4. The device according to claim 2, further comprising:

a pad unit,

the second interconnect electrically connecting the sensing amplifier circuit to the pad unit.

5. The device according to claim 4, wherein

the second interconnect is configured to input data to the sensing amplifier circuit, the input data being inputted from the pad unit.

6. The device according to claim 1, wherein

the second interconnect has a portion extending along a third direction perpendicular to the first direction and the second direction.

7. The device according to claim 1, wherein

at least a part of the first circuit unit is disposed between the first memory cell array unit and the substrate.

8. The device according to claim 1, wherein

a length of the first memory cell array unit along the first direction is shorter than a length of the second memory cell array unit along the first direction.

9. The device according to claim 1, wherein

electrical conductivity of a metal material included in the circuit layer is lower than electrical conductivity of a metal material included in the interconnect layer.

10. The device according to claim 1, wherein

a thermal stability of a metal material included in the circuit layer is higher than a thermal stability of a metal material included in the interconnect layer.

11. The device according to claim 1, further comprising:

a third contact interconnect; and

a fourth contact interconnect,

the interconnect layer further includes

a third interconnect extending along the first direction and

a fourth interconnect,

the memory layer further includes

a third memory cell array unit having at least a part juxtaposed to the first memory cell array unit along a third direction perpendicular to the first direction and the second direction, and including a plurality of memory cells electrically connected to the third interconnect, and

a fourth memory cell array unit having at least a part juxtaposed the third memory cell array along the first direction, juxtaposed to the second memory cell array unit along the third direction, and including a plurality of memory cells electrically connected to the third interconnect,

the circuit layer further includes a second circuit unit,

the third contact interconnect extends along the second direction between the third memory cell array unit and the fourth memory cell array unit, and electrically connecting a third end of the second circuit unit to the third interconnect,

the fourth contact interconnect extends along the second direction on an opposite side of the fourth memory cell array unit to the third contact interconnect, and electrically connecting a fourth end of the second circuit unit different from the third end to the fourth interconnect, and

a position of the first contact interconnect along the first direction and a position of the third contact interconnect along the first direction are disposed between a position of the second contact interconnect along the first direction and a position of the fourth contact interconnect along the first direction.

12. The device according to claim 11, wherein the first circuit unit includes a sensing amplifier circuit configured to detect electrical characteristics of the plurality of memory cells included in the third memory cell array unit and the plurality of memory cells included in the fourth memory cell array unit.

13. The device according to claim 11, further comprising:

a pad unit,

the fourth interconnect electrically connects the sensing amplifier circuit to the pad unit.

14. The device according to claim 11, wherein

the fourth interconnect has a portion extending along a third direction perpendicular to the first direction and the second direction.

15. The device according to claim 1, further comprising:

a third contact interconnect; and

a fourth contact interconnect,

the interconnect layer further includes

a third interconnect extending along the first direction and

a fourth interconnect,

the memory layer further includes

a third memory cell array unit having at least a part juxtaposed to the first memory cell array unit along a third direction perpendicular to the first direction and the second direction, and including a plurality of memory cells electrically connected to the third interconnect, and

a fourth memory cell array unit having at least a part juxtaposed the third memory cell array along the first direction, juxtaposed to the second memory cell array unit along the third direction, and including a plurality of memory cells electrically connected to the third interconnect,

the circuit layer further includes a second circuit unit,

the third contact interconnect extends along the second direction between the third memory cell array unit and the fourth memory cell array unit, and electrically connecting a third end of the second circuit unit to the third interconnect,

the fourth contact interconnect extends along the second direction on an opposite side of the fourth memory cell array unit to the third contact interconnect, and electrically connecting a fourth end of the second circuit unit different from the third end to the fourth interconnect,

a length of the first memory cell array unit along the first direction is equal to a length of the second memory cell array unit along the first direction, and

a length of the third memory cell array unit along the first direction is equal to a length of the fourth memory cell array unit along the first direction.

16. The device according to claim 15, wherein the first circuit unit includes a sensing amplifier circuit configured to detect electrical characteristics of the plurality of memory cells included in the third memory cell array unit and the plurality of memory cells included in the fourth memory cell array unit.

17. The device according to claim 15, further comprising:

a pad unit,

the fourth interconnect electrically connects the sensing amplifier circuit to the pad unit.

18. The device according to claim 15, wherein

the fourth interconnect has a portion extending along a third direction perpendicular to the first direction and the second direction.

19. The device according to claim 1, wherein

the first memory cell array unit includes

a stacked structure including a plurality of electrode films stacked along the second direction and an inter-electrode insulating film provided between the plurality of electrode films,

a semiconductor layer facing side surfaces of the plurality of electrode films along the second direction,

a memory layer provided between the semiconductor layer and the plurality of electrode films,

a first insulating film provided between the memory layer and the semiconductor layer, and

a second insulating film provided between the memory layer and the plurality of electrode films,

the semiconductor layer is electrically connected to the first interconnect, and

each of the plurality of memory cells included in the first memory cell array unit is provided in a portion where each of the plurality of electrode films faces the semiconductor layer.

20. The device according to claim 1, wherein

the first memory cell array unit includes

a first stacked structure including a plurality of first electrode films stacked along the second direction and a first inter-electrode insulating film provided between the plurality of first electrode films,

a first semiconductor pillar piercing the first stacked structure along the second direction,

a first memory layer provided between the first semiconductor pillar and the plurality of first electrode films,

a first inner insulating film provided between the first memory layer and the first semiconductor pillar, and

a first outer insulating film provided between the first memory layer and the plurality of electrode films,

the first semiconductor pillar is electrically connected to the first interconnect, and

each of the plurality of memory cells included in the first memory cell array unit is provided in a portion where each of the plurality of first electrode films intersect the first semiconductor pillar.