Non-Volatile Semiconductor Memory

• US 20120182798A1
• Filed: 03/23/2012
• Published: 07/19/2012
• Est. Priority Date: 03/08/2000
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hosono, Koji, Takeuchi, Ken, Imamiya, Kenichi, Nakamura, Hiroshi
• Granted Patent: US 8,472,268 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range.

Claims

1. A method of operating a non-volatile semiconductor memory, the method comprising:

loading first data;

outputting a busy signal and then beginning writing of the first data in accordance with an input of a write command;

loading second data after the busy signal is outputted during the first period; and

after the write command is again inputted, outputting the busy signal during a second period,

the writing of the first data being completed after the second busy signal begins to be outputted.

2. The method of claim 1, wherein:

each of the plurality of write/read circuits comprises a first latch and a second latch;

the first data is loaded to the first latch;

the first data in the first latch is transferred to the second latch during the first period when the busy signal is outputted;

the second data is loaded to the first latch after the first period when the busy signal is outputted; and

during the second period when the busy signal is outputted, an operation which writes the first data in the second latch into a corresponding memory cell is completed and the second data in the first latch is transferred to the second latch.

3. The method of claim 1, wherein:

a plurality of first data is loaded to respective first latches;

during the first period when the busy signal is outputted, the plurality of first data in the first latches is transferred to the respective second latches;

after the first period when the busy signal is outputted has elapsed, a plurality of second data is loaded to the respective first latches; and

during the second period when the busy signal is outputted, an operation which writes the plurality of first data in the second latches to respective memory cells is completed and the plurality of second data in the first latches is transferred to the respective second latches.

4. The method of claim 3, wherein when the plurality of first data is loaded to the respective first latches, a dummy write command is inputted and the plurality of first data is loaded to the respective first latches in sequence.

5. The method of claim 1, wherein the first period is shorter than the second period.

6. The method of claim 5, wherein a length of the second period depends on a time required for writing the first data to respective memory cells.

15. The method of claim 1, wherein the first data is stored in a lower page corresponding to a bit of a multi-level cell operation and the second data is stored in an upper page corresponding to another bit of the multi-level cell data operation.

7. A non-volatile semiconductor device comprising:

a memory cell array comprising non-volatile memory cells;

a plurality of write/read circuits configured to temporarily hold data to be written to the memory cell array and to control data to be read out from the memory cell array; and

a control circuit configured to control operations to be written to and read out from the memory cell array,

wherein each of the write/read circuits is selectively connected to the memory cell array, loads first data, begins a write operation of the first data in accordance with a write command, loads second data after a first period when a busy signal is outputted has elapsed, and outputs the busy signal during a second period after the write command has been inputted again, the first data being stored in a lower page corresponding to a bit of a multi-level cell operation and the second data being stored in an upper page corresponding to another bit of the multi-level cell data operation,

an operation of writing the first data to the memory cell being completed after the second period when the busy signal is outputted is begun.

8. The device of claim 7, wherein:

each of the plurality of write/read circuits comprises a first latch and a second latch;

the first data is loaded to the first latch;

the first data in the first latch is transferred to the second latch during the first period when the busy signal is outputted;

the second data is loaded to the first latch after the first period when the busy signal is outputted has elapsed; and

during the second period when the busy signal is outputted, an operation which writes the first data in the second latch into a corresponding memory cell is completed and the second data in the first latch is transferred to the second latch.

9. The device of claim 7, wherein:

a plurality of first data is loaded to respective first latches;

during the first period when the busy signal is outputted, the plurality of first data in the first latches is transferred to the respective second latches;

after the first period when the busy signal is outputted has elapsed, a plurality of second data is loaded to the respective first latches; and

during the second period when the busy signal is outputted, an operation which writes the plurality of first data in the second latches to the respective memory cells is completed and the plurality of second data in the first latches is transferred to the respective second latches.

10. The device of claim 7, wherein when the plurality of first data is loaded to the respective first latches, a dummy write command is inputted and the plurality of first data is loaded to the respective first latches in sequence.

11. The device of claim 7, wherein the first period is shorter than the second period.

12. The device of claim 11, wherein a length of the second period depends on a time required for writing the first data to the respective memory cells.

13. The device of claim 8, wherein the first and second latches are capable of bilaterally transferring data.

14. The device of claim 8, wherein each of the write/read circuits comprises:

a first transistor connected between the first latch and a sense node;

a second transistor connected between the second latch and the sense node; and

a third transistor connected between the sense node and a bit line.