Memory Architecture of 3D NOR Array

• US 20120182801A1
• Filed: 03/11/2011
• Published: 07/19/2012
• Est. Priority Date: 01/19/2011
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting
• Granted Patent: US 8,630,114 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A 3D memory device includes a plurality of ridge-shaped stacks of memory cells. Word lines are arranged over the stacks of memory cells. Bit lines structures are coupled to multiple locations along the stacks of memory cells. Source line structures are coupled to multiple locations along each of the semiconductor material strips of the stacks. The bit line structures and the source line structures are between adjacent ones of the word lines.

Claims

1. A memory device, comprising:

an integrated circuit substrate;

a plurality of stacks of semiconductor material strips extending out of the integrated circuit substrate, the plurality of stacks being ridge-shaped and including at least two semiconductor material strips separated by insulating material into different plane positions of a plurality of plane positions;

a plurality of word lines arranged orthogonally over the plurality of stacks;

a plurality of memory elements between surfaces of the plurality of stacks and the plurality of word lines;

a plurality of bit line structures coupled to multiple locations along each of the semiconductor material strips of the plurality of stacks; and

a plurality of source line structures coupled to multiple locations along each of the semiconductor material strips of the plurality of stacks,

wherein the plurality of bit line structures and the plurality of source line structures are between adjacent ones of the plurality of word lines.

2. The memory device of claim 1, wherein the plurality of memory elements respectively comprise a tunneling layer, a charge trapping layer and a blocking layer.

3. The memory device of claim 1, wherein the plurality of memory elements support volatile storage.

4. The memory device of claim 1, further comprising diodes, proximate to the plurality of bit line structures.

5. The memory device of claim 1, further comprising diodes, wherein the semiconductor material strips comprise n-type silicon of the diodes, and the diodes comprise a p-type region in the strips.

6. The memory device of claim 1, further comprising diodes, wherein the semiconductor material strips comprise n-type silicon of the diodes, and the diodes comprise a p-type plug in contact with the semiconductor material strips.

7. The memory device of claim 1, wherein a combined selection of a particular one of a plurality of bit lines, a particular one of a plurality of source lines, and a particular one of the plurality of word lines, identifies a particular memory element of the plurality of memory elements.

8. The memory device of claim 1, further comprising:

staircase structures coupling the plurality of source line structures to a plurality of source lines.

20. The memory device of claim 1, further comprising diodes, proximate to a plurality of bit line structures.

9. A memory device, comprising:

an integrated circuit substrate;

a 3D array of memory cells on the integrated circuit substrate, the 3D array including stacks of NOR memory cells,

a plurality of word lines arranged over the stacks of NOR memory cells;

a plurality of bit lines structures coupled to multiple locations along the stacks of NOR memory cells; and

a plurality of source line structures coupled to multiple locations along each of the semiconductor material strips of the plurality of stacks,

wherein the plurality of bit line structures and the plurality of source line structures are between adjacent ones of the plurality of word lines.

10. The memory device of claim 9, wherein the 3D array comprises memory elements in the interface regions that respectively comprise a tunneling layer, a charge trapping layer and a blocking layer.

11. The memory device of claim 9, wherein the 3D array comprises memory elements in the interface regions that support volatile storage.

12. The memory device of claim 9, further comprising diodes, proximate to the plurality of bit line structures.

13. The memory device of claim 9, further comprising diodes, wherein the stacks comprise n-type silicon of the diodes, and the diodes comprise a p-type region in the stacks.

14. The memory device of claim 9, further comprising diodes, wherein the stacks comprise n-type silicon of the diodes, and the diodes comprise a p-type plug in contact with the stacks.

15. The memory device of claim 9, wherein a combined selection of a particular one of a plurality of bit lines, a particular one of a plurality of source lines, and a particular one of the plurality of word lines, identifies a particular memory cell of the 3D array of memory cells.

16. The memory device of claim 9, further comprising:

staircase structures coupling the plurality of source line structures to a plurality of source lines.

17. A method of operating a 3D memory array, comprising:

biasing adjacent stacks of NOR memory cells in a 3D array, including

biasing bit lines coupled via diodes to multiple locations along the stacks of NOR memory cells.

18. The method of claim 17, wherein the stacks comprise memory elements that respectively comprise a tunneling layer, a charge trapping layer and a blocking layer.

19. The method of claim 17, wherein the stacks comprise memory elements that support volatile storage.