ARCHITECTURE FOR A 3D MEMORY ARRAY

• US 20120182804A1
• Filed: 09/26/2011
• Published: 07/19/2012
• Est. Priority Date: 01/19/2011
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: HUNG, CHUN-HSIUNG, Hung, Shuo-Nan, Hung, Ji-Yu, Huang, Shih-Lin, Wang, Fu-Tsang
• Granted Patent: US 8,724,390 B2
• Time in Patent Office: Days
• US Class Current: 365/185.13
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

Claims

1. An integrated circuit device, comprising:

a memory array; and

bias circuits that compensate for variations in threshold voltages corresponding to memory states of memory cells in the array by applying different bias conditions to selected bit lines.

2. The integrated circuit of claim 1, the memory array including a plurality of bit lines coupled via respective clamp transistors to corresponding data lines in a set of data lines, the data lines being coupled to corresponding sensing circuits, and wherein the bias circuits are responsive to timing signals during a read operation of a selected memory cell in the memory array, and include a precharge circuit connected to the data line, and a bias voltage source to apply a bias voltage to a control terminal of said clamp transistor that depends on the selected memory cell.

3. The integrated circuit of claim 2, wherein the memory array comprises a NAND array including a plurality of NAND strings having respective ground select transistors and string select transistors, ground select lines and string select lines, and word lines, and including a control circuit coupled to the memory array and the bias circuits, which for the read operation of the selected cell on a selected NAND string, causes a sequence including:

in a first time interval T0, charge the word lines coupled to the selected NAND string to target levels for read, and discharge the bit lines to a low reference voltage via the precharge circuit while the ground select transistor is off and the string select transistor is on;

in a second time interval T1, precharge the data line to a read reference voltage and apply a first clamp voltage to the clamp transistor that depends on the selected memory cell, whereby the data line and the addressing line for the selected NAND string are precharged to levels that depend on the selected memory cell;

in a third time interval T2, turn off the clamp transistor and disconnect the precharge circuit from the data line, turn on the ground select transistor while applying a read bias voltage to the source line;

in a fourth time interval T3, apply a second clamp voltage, higher than the first claim voltage, to the clamp transistor that depends on the selected memory cell, and sense the level of the data line to indicate a value of data stored in the selected memory cell.

4. The integrated circuit of claim 3, wherein the bias circuits include a boost circuit coupled to the data line, which is responsive to timing signals during the read operation, to capacitively boost a voltage on the data line by a boost amount.

5. The integrated circuit of claim 3, wherein the bias circuits include a boost circuit coupled to the data line, which is responsive to timing signals during the read operation, to capacitively boost a voltage on the data line by a boost amount, and a boost voltage source coupled to the boost circuit to set the boost amount that depends on the selected memory cell, and wherein the sequence includes in or before the fourth time interval, apply a boost voltage to boost the data line before sensing the level of the data line.

6. The integrated circuit of claim 1, wherein the word line voltages applied to the memory cells in the array are substantially the same during the different bias conditions.

7. The integrated circuit of claim 1, wherein the memory array includes a plurality of blocks, blocks in the plurality of blocks comprising a plurality of levels L(z), levels L(z) in the plurality of levels including respective two dimensional arrays of memory cells, respective two dimensional arrays including a plurality of word lines and a plurality of local bit lines coupled to corresponding memory cells in the array;

and

a plurality of global bit lines, global bit lines in the plurality of global bit lines including a plurality of connectors, connectors in the plurality of connectors coupled to a given global bit line being coupled to corresponding local bit lines in the plurality of blocks, the bias circuits coupled to the plurality of global bit lines.

8. An integrated circuit, comprising:

a plurality of blocks, blocks in the plurality of blocks comprising a plurality of levels L(z), levels L(z) in the plurality of levels including respective two dimensional arrays of memory cells, respective two dimensional arrays including a plurality of local bit lines coupled to corresponding memory cells in the array;

a plurality of global bit lines, global bit lines in the plurality of global bit lines including a plurality of connectors, connectors in the plurality of connectors coupled to a given global bit line being coupled to corresponding local bit lines in the plurality of blocks, and wherein the corresponding local bit line in one of the plurality of blocks is on a different level L(z) than the corresponding local bit line in another of the plurality of ii blocks; and

switch circuits coupled to the plurality of global bit lines, the switch circuits configured to apply respective bias voltages to corresponding global bit lines depending on the level L(z) of a selected memory cell.

9. The integrated circuit of claim 8, wherein there are N levels L(z) (level index z=1 to N) in each of the plurality of blocks, and the connectors are arranged on each global bit line in the plurality of global bit lines such that a statistical function of level indexes for the levels L(z) of the corresponding local bit lines is equal to a constant.

10. The integrated circuit of claim 9, wherein a level in the plurality of levels in a given block in the plurality of blocks includes a contact pad connected to a connector in the plurality of connectors on a corresponding global bit line, and switches selectively connecting the contact pad to the corresponding local bit line.

11. The integrated circuit of claim 10, wherein arrays comprise NAND arrays, and the switches comprise string select transistors.

12. The integrated circuit of claim 8, including bias circuits coupled to the switch circuits that compensate for variations in threshold voltages corresponding to memory states of selected memory cells, based on the level L(z) of the selected memory cell.

13. The integrated circuit of claim 8, including buffers coupled to the plurality of global bit lines and to the switch circuits.

14. An integrated circuit comprising:

a memory array including a plurality of levels of memory cells, levels in the plurality of levels including local bit lines and memory cells coupled to the local bit lines;

global bit lines coupled to corresponding sets of local bit lines in the array;

decoding circuitry to select memory cells in the plurality of levels; and

bias circuits coupled to the global bit lines for providing selected bias voltages, and responsive to control signals to select a bias voltage for the global bit line that corresponds to the level of a selected memory cell.

15. The integrated circuit of claim 14, wherein the set of local bit lines coupled to a given one of the global bit lines includes local bit lines in more than one level of the memory array.

16. The integrated circuit of claim 14, wherein there are N levels L(z) (level index z=1 to N) in the memory array, and sets of local bit lines coupled to respective global bit lines in the plurality of global bit lines are arranged such that a statistical function (e.g. a sum or a mean) of level indexes for the levels L(z) of the set local bit lines corresponding to each global bit line in the plurality of global bit lines, is equal to a constant.

17. The integrated circuit of claim 16, wherein a level in the plurality of levels in a memory array includes a contact pad connected to a connector on a corresponding global bit line, and switches selectively connecting the contact pad to the corresponding local bit line.

18. The integrated circuit of claim 14, the global bit lines being coupled via respective clamp transistors to corresponding data lines in a set of data lines, the data lines being coupled to corresponding sensing circuits, and wherein the bias circuits are responsive to timing signals during a read operation of a selected memory cell in the memory array, and include a precharge circuit connected to the data line, and a bias voltage source to apply a bias voltage to a control terminal of said clamp transistor that depends on the level of the selected memory cell.

19. The integrated circuit of claim 18, wherein the memory array comprises a NAND array including a plurality of NAND strings having respective ground select transistors and string select transistors, ground select lines and string select lines, and word lines, and including a control circuit coupled to the memory array and the bias circuits, which for the read operation of the selected cell on a selected NAND string, causes a sequence including:

in a first time interval T0, charge the word lines coupled to the selected NAND string to target levels for read, and discharge the global bit lines to a low reference voltage via the precharge circuit while the ground select transistor is off and the string select transistor is on;

in a second time interval T1, precharge the data line to a read reference voltage and apply a first clamp voltage to the clamp transistor that depends on the selected memory cell, whereby the data line and the bit line for the selected NAND string are precharged to levels that depend on the selected memory cell;

in a third time interval T2, turn off the clamp transistor and disconnect the precharge circuit from the data line, turn on the ground select transistor while applying a read bias voltage to the source line;

in a fourth time interval T3, apply a second clamp voltage, higher than the first claim voltage, to the clamp transistor that depends on the selected memory cell, and sense the level of the data line to indicate a value of data stored in the selected memory cell.

20. The integrated circuit of claim 18, wherein the bias circuits include a boost circuit coupled to the data line, which is responsive to timing signals during the read operation, to capacitively boost a voltage on the data line by a boost amount.

21. The integrated circuit of claim 18, wherein the bias circuits include a boost circuit coupled to the data line, which is responsive to timing signals during the read operation, to capacitively boost a voltage on the data line by a boost amount, and a boost voltage source coupled to the boost circuit to set the boost amount that depends on the selected memory cell, and wherein the sequence includes in or before the fourth time interval, apply a boost voltage to boost the data line before sensing the level of the data line.