PROCESSOR MODE LOCKING

• US 20120185688A1
• Filed: 01/09/2012
• Published: 07/19/2012
• Est. Priority Date: 01/13/2011
• Status: Abandoned Application

• Current Assignee: Google Inc. (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Thornton, Andrew, Lee, Jung-Ik
• Application Number:
  US13/346,547
• Publication Number:
  US 20120185688A1
• Time in Patent Office: Days
• US Class Current: 713/100
• CPC Class Codes: G06F 2009/45587 Isolation or security of virtual machine instances
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

Implementations of the present disclosure are directed to a method, system and computer-readable medium for operating a processor in a data processing apparatus in a first processing mode; setting one or more control bits of a control register of the processor to configure the processor to operate in a different second processing mode; providing a virtual register in a virtual machine executing on the data processing apparatus, the virtual register having one or more locking bits corresponding to the control bits of the control register; setting a value of the one or more locking bits of the virtual register; and in response to setting the value of the one or more locking bits, preventing the processor from being configured to operate in the first processing mode.

Claims

1. A method implemented by a data processing apparatus, the method comprising:

operating a processor in the data processing apparatus in a first processing mode;

setting one or more control bits of a control register of the processor to configure the processor to operate in a different second processing mode;

providing a virtual register in a virtual machine executing on the data processing apparatus, the virtual register having one or more locking bits corresponding to the control bits of the control register;

setting a value of the one or more locking bits of the virtual register; and

in response to setting the value of the one or more locking bits, preventing the processor from being configured to operate in the first processing mode.

2. The method of claim 1, further comprising intercepting an attempt to change the value of the one or more control bits of the control register.

3. The method of claim 1, wherein setting the value of the one or more locking bits further includes indicating a monitoring of the value of the one or more control bits.

4. The method of claim 1, wherein operating the processor further includes operating the processor in the first processing mode during booting of an operating system of the processor.

5. The method of claim 1, wherein the first processing mode is a 16-bit processing mode and the second processing mode is a 32-bit processing mode.

6. The method of claim 1, wherein the first processing mode is a 16-bit processing mode and the second processing mode is a 64-bit processing mode.

7. A system comprising:

a computer readable medium having instructions stored thereon; and

a data processing apparatus configured to execute the instructions to perform operations comprising;

operating a processor in the data processing apparatus in a first processing mode;

setting one or more control bits of a control register of the processor to configure the processor to operate in a different second processing mode;

providing a virtual register in a virtual machine executing on the data processing apparatus, the virtual register having one or more locking bits corresponding to the one or more control bits of the control register;

setting a value of the one or more locking bits of the virtual register; and

in response to setting the value of the one or more locking bits, preventing the processor from being configured to operate in the first processing mode.

8. The system of claim 7, the operations further comprising intercepting an attempt to change the value of the one or more control bits of the control register.

9. The system of claim 7, wherein setting the value of the one or more locking bits further includes indicating a monitoring of the value of the one or more control bits.

10. The method of claim 7, wherein operating the processor further includes operating the processor in the first processing mode during booting of an operating system of the processor.

11. The system of claim 7, wherein the first processing mode is a 16-bit processing mode and the second processing mode is a 32-bit processing mode.

12. The system of claim 7, wherein the first processing mode is a 16-bit processing mode and the second processing mode is a 64-bit processing mode.

13. The system of claim 7, wherein in response to setting the value of the one or more locking bits, the operations further include configuring the processor to operate only in the second processing mode.

14. A computer program product stored in one or more storage media for controlling a processing mode of a data processing apparatus, the computer program product being executable by the data processing apparatus to cause the data processing apparatus to perform operations comprising:

operating a processor in the data processing apparatus in a first processing mode;

setting one or more control bits of a control register of the processor to configure the processor to operate in a different second processing mode;

providing a virtual register in a virtual machine executing on the data processing apparatus, the virtual register having one or more locking bits corresponding to the one or more control bits of the control register;

setting a value of the one or more locking bits of the virtual register; and

in response to setting the value of the one or more locking bits, preventing the processor from being configured to operate in the first processing mode.

15. The computer program product of claim 14, the operations further comprising intercepting an attempt to change the value of the one or more control bits of the control register.

16. The computer program product of claim 14, wherein setting the value of the one or more locking bits further includes indicating a monitoring of the value of the one or more control bits.

17. The method of claim 14, wherein operating the processor further includes operating the processor in the first processing mode during booting of an operating system of the processor.

18. The computer program product of claim 14, wherein the first processing mode is a 16-bit processing mode and the second processing mode is a 32-bit processing mode.

19. The computer program product of claim 14, wherein the first processing mode is a 16-bit processing mode and the second processing mode is a 64-bit processing mode.

20. The computer program product of claim 14, wherein in response to setting the value of the one or more locking bits, the operations further include configuring the processor to operate only in the second processing mode.