Saving Power in Computing Systems with Redundant Service Processors

• US 20120185726A1
• Filed: 01/14/2011
• Published: 07/19/2012
• Est. Priority Date: 01/14/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Duron, Mike C., McLaughlin, Mark D.
• Granted Patent: US 8,661,290 B2
• Time in Patent Office: Days
• US Class Current: 714/11
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 11/2048 where the redundant components share neither address space nor persistent storage
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3062 where the monitored property is the power consumption power management in a computing system G06F1/3203

Abstract

A mechanism is provided for saving power in redundant service processors of the data processing system. A redundant service processor places a plurality of components into a low power state in response to receiving a primary control signal from a primary service processor within a first predetermined time period. The redundant service processor monitors for a signal within a second predetermined time period from the primary service processor. The redundant service processor determines whether the signal is a heartbeat signal or an activate signal in response to receiving the signal from the primary service processor within the second predetermined time period. Responsive to receiving the activate signal, the redundant service processor wakes-up the plurality of components that are in the low-power state in order for the redundant service processor to collect data and recover the data processing system in an event of a failure.

Claims

1. A method, in a data processing system, for saving power in redundant service processors of the data processing system, the method comprising:

responsive to receiving a primary control signal from a primary service processor within a first predetermined time period, placing, by the redundant service processor, a plurality of components into a low power state;

monitoring, by the redundant service processor, for a signal within a second predetermined time period from the primary service processor;

responsive to receiving the signal from the primary service processor within the second predetermined time period, determining, by the redundant service processor, whether the signal is a heartbeat signal or an activate signal; and

responsive to receiving the activate signal, waking-up, by the redundant service processor, the plurality of components that are in the low-power state in order for the redundant service processor to collect data and recover the data processing system in an event of a failure.

2. The method of claim 1, wherein the plurality of components excludes an Ethernet controller of the redundant service processor.

3. The method of claim 1, wherein an Ethernet controller of the redundant service processor receives the primary control signal and sends the signal to a power switch and wherein the power switch places the plurality of components as well as itself into the low power state.

4. The method of claim 1, wherein an Ethernet controller of the redundant service processor receives the activate signal and sends the signal to a power switch and wherein the power switch of the redundant service processor wakes-up the plurality of components as well as itself.

5. The method of claim 1, further comprising:

responsive to a failure to receive the primary control signal from the primary service processor within the first predetermined time period, waking-up, by the redundant service processor, the plurality of components that are in the low-power state in order for the redundant service processor to collect the data and recover the data processing system in the event of a failure.

6. The method of claim 1, further comprising:

responsive to a failure to receive the signal from the primary service processor within the second predetermined time period, waking-up, by the redundant service processor, the plurality of components that are in the low-power state in order for the redundant service processor to collect the data and recover the data processing system in the event of a failure.

7. The method of claim 1, further comprising:

responsive to receiving the heartbeat signal, continuing to monitor, by the redundant service processor, for another signal within a third predetermined time period from the primary service processor.

8. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:

responsive to receiving a (primary control signal from a primary service processor within a first predetermined time period, place a plurality of components into a tow power state;

monitor for a signal within a second predetermined time period from the primary service processor;

responsive to receiving the signal from the primary service processor within the second predetermined time period, determine whether the signal is a heartbeat signal or an activate signal; and

responsive to receiving the activate signal, wake-up the plurality of components that are in the low-power state in order for the redundant service processor to collect data and recover the data processing system in an event of a failure.

9. The computer program product of claim 8, wherein the plurality of components excludes an Ethernet controller of the redundant service processor.

10. The computer program product of claim 8, wherein an Ethernet controller of the redundant service processor receives the primary control signal and sends the signal to a power switch and wherein the power switch places the plurality of components as well as itself into the low power state.

11. The computer program product of claim 8, wherein an Ethernet controller of the redundant service processor receives the activate signal and sends the signal to a power switch and wherein the power switch of the redundant service processor wakes-up the plurality of components as well as itself.

12. The computer program product of claim 8, wherein the computer readable program further causes the computing device to:

responsive to a failure to receive the primary control signal from the primary service processor within the first predetermined time period, wake-up the plurality of components that are in the low-power state in order for the redundant service processor to collect the data and recover the data processing system in the event of a failure.

13. The computer program product of claim 8, wherein the computer readable program further causes the computing device to:

responsive to a failure to receive the signal from the primary service processor within the second predetermined time period, wake-up the plurality of components that are in the low-power state in order for the redundant service processor to collect the data and recover the data processing system in the event of a failure.

14. The computer program product of claim 8, wherein the computer readable program further causes the computing device to:

responsive to receiving the heartbeat signal, continue to monitor for another signal within a third predetermined time period from the primary service processor.

15. An apparatus, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises instructions which, when executed b the processor, cause the processor to;

responsive to receiving a primary control signal from a primary service processor within a first predetermined time period, place a plurality of components into a low power state;

monitor for a signal within a second predetermine(period from the primary service processor;

responsive to receiving the signal from the primary service processor within the second predetermined time period, determine whether the signal is a heartbeat signal or an activate signal; and

responsive to receiving the activate signal, wake-up the plurality of components that are in the tow-power state in order for the redundant service processor to collect data and recover the data processing system in an event of a failure.

16. The apparatus of claim 15, wherein the plurality of components excludes an Ethernet controller of the redundant service processor.

17. The apparatus of claim 15, wherein an Ethernet controller of the redundant service processor receives the primary control signal and sends the signal to a power switch and wherein the power switch places the plurality of components as well as itself into the tow power state.

18. The apparatus of claim 15, wherein an Ethernet controller of the redundant service processor receives the activate signal and sends the signal to a power switch and wherein the power switch of the redundant service processor wakes-up the plurality of components as well as itself.

19. The apparatus of claim 15, wherein the instructions further cause the processor to:

responsive to a failure to receive the primary control signal from the primary service processor within the first predetermined time period, wake-up the plurality of components that are in the low-power state in order for the redundant service processor to collect the data and recover the data processing system in the event of a failure.

20. The apparatus of claim 15, wherein the instructions further cause the processor to:

responsive to a failure to receive the signal from the primary service processor within die second predetermined time period, wake-up the plurality of components that are in the low-power state in order for the redundant service processor to collect the data and recover the data processing system in the event of a failure.

21. The apparatus of claim 15, wherein the instructions further cause the processor to:

responsive to receiving the heartbeat signal, continue to monitor for another signal within a third predetermined time period from the primary service processor.