PIXEL ARRAY AND IMAGE SENSOR INCLUDING THE SAME

• US 20120187304A1
• Filed: 01/03/2012
• Published: 07/26/2012
• Est. Priority Date: 01/26/2011
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: HA, Man Lyun, Lee, Ju Il, Choi, Sun
• Granted Patent: US 8,895,936 B2
• Time in Patent Office: Days
• US Class Current: 250/370.08
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

A pixel array and an image sensor including the pixel array having improved sensitivity and can drive pixels with high resolution, according to embodiments. In embodiments, a pixel array may include a plurality of pixels having a pixel area and a logic area. The pixel array may include at least one of: (1) A photoelectric conversion unit in the pixel area of each of the pixels. (2) A pixel-area transistor disposed at a side of the photoelectric conversion unit in the pixel area. (3) A metal-0 layer on the pixel-area transistor. (4) A metal-1 layer on and/or over the metal-0 layer. (5) A light reception unit on and/or over the metal-1 layer, with the metal-1 layer being the top metal layer in the pixel area.

Claims

1. A pixel array comprising a plurality of pixels having a pixel area and a logic area, the pixel array comprising:

a photoelectric conversion unit at the pixel area of each of the pixels;

a pixel-area transistor disposed in the pixel area at a side of the photoelectric conversion unit;

a metal-0 layer over the pixel-area transistor;

a metal-1 layer over the metal-0 layer; and

a light reception unit over the metal-1 layer,

wherein the metal-1 layer is a top metal of the pixel area.

2. The pixel array according to claim 1, wherein the metal-0 layer electrically connects pixel-area transistors of the pixels.

3. The pixel array according to claim 1, wherein the metal-0 layer has a thickness of about 500 Å

to about 2,000 Å

.

4. The pixel array according to claim 3, further comprising a first photodiode, a second photodiode, a first transfer transistor, a second transfer transistor, a reset transistor, a source follower, and a select transistor,

wherein the metal-0 layer comprises:

a first metal-0 layer connecting each gate of the first transfer transistors for the plurality of pixels;

a second metal-0 layer connecting each gate of the select transistors for the plurality of pixels;

a third metal-0 layer connecting each gate of the second transfer transistor for the plurality of pixels, and

a fourth metal-0 layer connecting each gate of the reset transistor for the plurality of pixels.

5. The pixel array according to claim 4, wherein the first and second photodiodes share a floating diffusion area.

6. The pixel array according to claim 3, further comprising a first transfer transistor, a second transfer transistor, a third transfer transistor, a fourth transfer transistor, a reset transistor, and a drive transistor,

wherein the metal-0 layer comprises:

a first metal-0 layer connecting each gate of the first transfer transistors for the plurality of pixels;

a second metal-0 layer connecting each gate of the second transfer transistors for the plurality of pixels;

a third metal-0 layer connecting each gate of the third transfer transistors for the plurality of pixels;

a fourth metal-0 layer connecting each gate of the fourth transfer transistors for the plurality of pixels; and

a fifth metal-0 layer connecting each gate of the reset transistors for the plurality of pixels.

7. The pixel array according to claim 3, further comprising a reset transistor, a select transistor, and a drive transistor,

wherein the metal-0 layer comprises:

a first metal-0 layer connecting each gate of the select transistors for the plurality of pixels; and

a second metal-0 layer connecting each gate of the reset transistors for the plurality of pixels.

8. The pixel array according to claim 1, wherein no metal layer exists between the metal-1 layer and the light reception unit, and no metal layer exist between the metal-0 layer and the metal-1 layer.

9. The pixel array according to claim 1, wherein the metal-0 layer functions as a global interconnection (GIC) for electrically connecting pixel-area transistors of the pixels.

10. An image sensor comprising:

a pixel array comprising a plurality of pixels having a pixel area and a logic area; and

a pixel gate driver at a side of the pixel array,

wherein the pixel array comprises;

a photoelectric conversion unit at the pixel area of each of the pixels;

a pixel-area transistor disposed in the pixel area at a side of the photoelectric conversion unit;

a metal-0 layer on the pixel-area transistor;

a metal-1 layer on the metal-0 layer, and

a light reception unit on the metal-1 layer,

wherein the metal-1 layer is a top metal of the pixel area.

11. The image sensor according to claim 10, wherein the pixel gate driver comprises:

a first pixel gate driver at one side of the pixel array; and

a second pixel gate driver at another side of the pixel array.

12. The image sensor according to claim 10, further comprising a readout IC disposed under a pixel chip including the pixel array and electrically connected with the pixel array.

13. The image sensor according to claim 10, further comprising a through via making contact with the metal-1 layer of the pixel array and electrically connected with the readout IC.

14. The image sensor according to claim 10, wherein when the image sensor is driven, a pre-emphasis is added.

15. The image sensor according to claim 10, wherein the metal-0 layer electrically connects pixel-area transistors of the pixels.

16. The image sensor according to claim 10, wherein the metal-0 layer has a thickness of approximately 500 Å

to approximately 2,000 Å

.

17. The image sensor according to claim 10, wherein the pixel array comprises a first photodiode, a second photodiode, a first transfer transistor, a second transfer transistor, a reset transistor, a source follower, and a select transistor,

wherein the metal-0 layer comprises:

a first metal-0 layer connecting each gate of the first transfer transistors for the plurality of pixels;

a second metal-0 layer connecting each gate of the select transistors for the plurality of pixels,

a third metal-0 layer connecting each gate of the second transfer transistors for the plurality of pixels, and

a fourth metal-0 layer connecting each gate of the reset transistors for the plurality of pixels.

18. The image sensor according to claim 17, wherein the first and second photodiodes share a floating diffusion area.

19. The image sensor according to claim 10, wherein the pixel array comprises a first transfer transistor, a second transfer transistor, a third transfer transistor, a fourth transfer transistor, a reset transistor, and a drive transistor,

wherein the metal-0 layer comprises:

a first metal-0 layer connecting each gate of the first transfer transistors for the plurality of pixels;

a second metal-0 layer connecting each gate of the second transfer transistors for the plurality of pixels;

a third metal-0 layer connecting each gate of the third transfer transistors for the plurality of pixels,

a fourth metal-0 layer connecting each gate of the fourth transfer transistors for the plurality of pixels, and

a fifth metal-0 layer connecting each gate of the reset transistors for the plurality of pixels.

20. The image sensor according to claim 10, wherein the pixel array comprises a reset transistor, a select transistor, and a drive transistor, and

wherein the metal-0 layer comprises:

a first metal-0 layer connecting each gate of the select transistors for the plurality of pixels; and

a second metal-0 layer connecting each gate of the reset transistors for the plurality of pixels.