SEMICONDUCTOR DEVICE INCLUDING AN EPITAXY REGION

• US 20120187459A1
• Filed: 01/20/2011
• Published: 07/26/2012
• Est. Priority Date: 01/20/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fan, Wei-Han, Lin, Yun Jing, Huang, Yimin, Pan, Te-Jen, Lin, Yu-Hsien, Shen, Hsiang-Ku, Wang, Tzu-Chung
• Granted Patent: US 9,595,477 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

Claims

1. A method comprising:

providing a substrate;

forming a first spacer material layer abutting a gate structure on the substrate, wherein the first spacer material includes silicon and carbon;

forming a second spacer material layer overlying the first spacer material layer;

etching the first spacer material layer and the second spacer material layer concurrently to form a first and a second spacer respectively; and

forming an epitaxy region on the substrate interfacing the first and second spacers.

2. The method of claim 1, further comprising:

forming a low-dose drain region prior to forming the first spacer material layer.

3. The method of claim 1, further comprising:

removing the second spacer after forming the epitaxy region.

4. The method of claim 3, further comprising:

forming an interlayer dielectric (ILD) layer on the substrate after removing the second spacer, wherein the ILD layer includes an interface with the first spacer.

5. The method of claim 1, wherein the forming the first spacer material layer includes depositing SiCN.

6. The method of claim 1, wherein the forming the second spacer material layer includes depositing silicon nitride.

7. The method of claim 1, wherein the etching the first spacer material layer and the second spacer material layer concurrently includes removing the first spacer material layer from a top surface of the gate structure and exposing a region of the substrate wherein the epitaxy region will be formed.

8. The method of claim 1, wherein the gate structure includes polysilicon.

9. The method of claim 8, wherein the gate structure includes a hard mask layer overlying the polysilicon.

10. The method of claim 1, wherein the forming the first spacer material layer includes forming a conformal layer, which is not etched prior to forming the second spacer material layer.

11. The method of claim 1, further comprising:

removing the gate structure from the substrate, wherein the removing the gate structure provides a trench having sidewalls defined by the first spacer material.

12. A method, comprising:

providing a semiconductor substrate;

forming a dummy gate structure on the semiconductor substrate;

forming a spacer element liner layer on the sidewalls of the dummy gate structure, wherein the spacer element liner layer includes silicon and carbon;

forming a main spacer abutting the spacer element liner layer;

growing an epitaxy region on the semiconductor substrate adjacent the spacer element liner layer and the main spacer;

removing the main spacer after growing the epitaxy region; and

removing the dummy gate structure after removing the main spacer, wherein the removing the dummy gate structure forms a trench having walls defined by the spacer element liner layer.

13. The method of claim 12, wherein the growing the epitaxy region includes creating an interface between the epitaxy region and the spacer element liner layer.

14. The method of claim 12, wherein the forming the spacer element liner layer includes forming a layer of substantially uniform thickness having a substantially L-shape.

15. The method of claim 12, wherein the spacer element liner layer is not etched prior to the forming the main spacer.

16. The method of claim 12, further comprising:

forming a gate structure in the trench including a gate dielectric and an electrode including metal, wherein the gate structure has an interface with the spacer element liner layer.

17. A device, comprising:

a semiconductor substrate;

a gate structure on the semiconductor substrate;

an epitaxy region disposed on the semiconductor substrate and adjacent the gate structure;

a spacer element having a substantially uniform thickness, abutting the gate structure, and having at least one interface with the epitaxy region; and

an interlayer dielectric layer on the substrate and overlying the spacer element.

18. The device of claim 17, wherein the spacer element includes silicon and carbon.

19. The device of claim 17, wherein the epitaxy region is at least one of silicon germanium and silicon epitaxy.

20. The device of claim 17, wherein the substantially uniform thickness is less than approximately 100 Angstroms.