INTEGRATION OF STRUCTURALLY-STABLE ISOLATED CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER (CMUT) ARRAY CELLS AND ARRAY ELEMENTS

• US 20120187508A1
• Filed: 03/13/2012
• Published: 07/26/2012
• Est. Priority Date: 10/02/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Johnson, Peter, Percin, Gokhan, Mostafazadeh, Shahram, Adler, Steven J.
• Granted Patent: US 8,563,345 B2
• Time in Patent Office: Days
• US Class Current: 257/416
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: G01N 29/2406 Electrostatic or capacitive probes, e.g. electret or cMUT-probes
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer.

Claims

1. A method for forming a capacitive micromachined ultrasonic transducer (CMUT), the method comprising:

forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure, each CMUT element comprising multiple CMUT cells, the first SOI structure comprising a first handle wafer, a first buried layer, and a first active layer;

forming a membrane over the CMUT elements; and

forming electrical contacts through the first handle wafer and the first buried layer, the electrical contacts in electrical connection with the CMUT elements.

2. The method of claim 1, wherein forming the electrical contacts comprises:

forming vias through the first handle wafer and the first buried layer; and

depositing at least one conductive material into the vias.

3. The method of claim 2, wherein forming the vias comprises forming one via to each CMUT cell in each CMUT element.

4. The method of claim 2, wherein forming the vias comprises forming one via to each CMUT element.

5. The method of claim 2, wherein forming the vias comprises:

forming multiple recesses in the first handle wafer; and

forming the vias within the recesses.

6. The method of claim 2, wherein forming the vias comprises:

reducing a thickness of the first handle wafer; and

forming the vias through the reduced-thickness first handle wafer and the first buried layer.

7. The method of claim 2, wherein depositing the at least one conductive material comprises electroplating copper into the vias.

8. The method of claim 1, wherein forming the membrane comprises:

bonding a second SOI structure to the first SOI structure, the second SOI structure comprising a second handle wafer, a second buried layer, and a second active layer; and

removing the second handle wafer and the second buried layer, the membrane comprising the second active layer.

9. The method of claim 8, further comprising:

forming an oxide layer over the CMUT cells and the CMUT elements before bonding the second SOI structure to the first SOI structure.

10. A method for forming a capacitive micromachined ultrasonic transducer (CMUT), the method comprising:

forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure, each CMUT element comprising multiple CMUT cells, the first SOI structure comprising a first handle wafer, a first buried layer, and a first active layer;

forming an oxide layer over the first active layer;

bonding a second SOI structure to the oxide layer, the second SOI structure comprising a second handle wafer, a second buried layer, and a second active layer;

forming electrical contacts through the first handle wafer and the first buried layer, the electrical contacts in electrical connection with the CMUT elements; and

removing the second handle wafer and the second buried layer to form a membrane over the CMUT elements.

11. The method of claim 10, wherein forming the electrical contacts comprises:

forming vias through the first handle wafer and the first buried layer; and

depositing at least one conductive material into the vias.

12. The method of claim 11, wherein forming the vias comprises forming one via to each CMUT cell in each CMUT element.

13. The method of claim 11, wherein forming the vias comprises forming one via to each CMUT element.

14. The method of claim 11, wherein forming the vias comprises:

forming multiple recesses in the first handle wafer; and

forming the vias within the recesses.

15. The method of claim 11, wherein forming the vias comprises:

reducing a thickness of the first handle wafer; and

forming the vias through the reduced-thickness first handle wafer and the first buried layer.

16. An integrated circuit device comprising:

a semiconductor-on-insulator (SOI) structure comprising a handle wafer, a buried layer, and an active layer;

multiple capacitive micromachined ultrasonic transducer (CMUT) elements at least partially within the active layer, each CMUT element comprising multiple CMUT cells;

a membrane over the CMUT elements; and

electrical contacts through the handle wafer and the buried layer, the electrical contacts in electrical connection with the CMUT elements.

17. The integrated circuit device of claim 16, wherein the electrical contacts comprise at least one conductive material in vias through the handle wafer and the buried layer.

18. The integrated circuit device of claim 17, wherein the electrical contacts comprise one electrical contact to each CMUT cell in each CMUT element.

19. The integrated circuit device of claim 17, wherein the electrical contacts comprise one electrical contact to each CMUT element.

20. The integrated circuit device of claim 17, wherein:

the handle wafer comprises multiple recesses; and

the vias are located within the recesses.